Simulation Results: spi_host

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.48 %
  • code
  • 91.30 %
  • assert
  • 94.90 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 90.000s 15171.237us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 31.925us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 190.494us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 46.820us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 55.642us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 93.083us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 190.494us 1 1 100.00
spi_host_csr_aliasing 2.000s 55.642us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 22.830us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 28.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 65.576us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 51.462us 1 1 100.00
spi_host_error_cmd 1.000s 28.634us 1 1 100.00
spi_host_event 16.000s 1549.377us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 5.000s 730.847us 1 1 100.00
speed 1 1 100.00
spi_host_speed 5.000s 730.847us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 5.000s 730.847us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 243.000s 13372.879us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 13.000s 619.770us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 113.667us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 5.000s 730.847us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 5.000s 730.847us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 90.000s 15171.237us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 90.000s 15171.237us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 48.616us 1 1 100.00
spien 1 1 100.00
spi_host_spien 10.000s 3691.335us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 39.000s 2743.099us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 139.089us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 51.462us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 53.670us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 83.051us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 87.940us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 87.940us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 31.925us 1 1 100.00
spi_host_csr_rw 1.000s 190.494us 1 1 100.00
spi_host_csr_aliasing 2.000s 55.642us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 23.194us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 31.925us 1 1 100.00
spi_host_csr_rw 1.000s 190.494us 1 1 100.00
spi_host_csr_aliasing 2.000s 55.642us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 23.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 184.285us 1 1 100.00
spi_host_sec_cm 1.000s 135.824us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 184.285us 1 1 100.00