Simulation Results: sram_ctrl/main

 
09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.91 %
  • code
  • 94.83 %
  • assert
  • 98.10 %
  • func
  • 94.80 %
  • block
  • 94.14 %
  • line
  • 95.27 %
  • branch
  • 92.21 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 2847.689us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 52.680us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.005us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 220.435us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.414us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 2306.491us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.005us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.414us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 315.000s 29277.139us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 114.000s 14959.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 29.000s 10233.377us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 110.000s 2737.382us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 171.000s 4449.752us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 69.000s 36126.118us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 27.000s 10991.187us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 38.000s 26873.226us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.000s 1419.923us 1 1 100.00
sram_ctrl_partial_access_b2b 435.000s 27392.879us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 682.051us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 3189.216us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 9544.247us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1349.639us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1396.899us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 7.000s 2847.689us 1 1 100.00
sram_ctrl_partial_access 8.000s 1419.923us 1 1 100.00
sram_ctrl_access_during_key_req 69.000s 36126.118us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 193.000s 35611.976us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 26.904us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 130.711us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 130.711us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 52.680us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.005us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.414us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 52.680us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.005us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 16.414us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 3740.914us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 858.665us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 185.970us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 858.665us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 185.970us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1349.639us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1349.639us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.005us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 38.000s 26873.226us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 38.000s 26873.226us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 38.000s 26873.226us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 27.000s 10991.187us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 3740.914us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 2847.689us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 2847.689us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 38.000s 26873.226us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 858.665us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 27.000s 10991.187us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 858.665us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 858.665us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 2847.689us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 858.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 19.000s 3630.374us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 100967653467823368680199634216092551973360097276479653098872481620673870028967 None
sram_ctrl_mubi_enc_err 8210004134691817810946725971079880232051683244062570177171492447762373119422 None