Simulation Results

Simulation Results: uart

09/09/2026 15:31:43 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.29 %

code
73.47 %

assert
97.69 %

func
90.69 %

block
98.41 %

line
98.95 %

branch
96.87 %

toggle
73.08 %

FSM
25.00 %

Validation stages

V1		100.00%
V2		90.91%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.000s	155.005us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	30.203us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	42.330us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	146.122us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	47.545us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	31.914us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	42.330us	1	1	100.00
	uart_csr_aliasing	1.000s	47.545us	1	1	100.00

20/22 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	38.000s	24107.157us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.000s	155.005us	1	1	100.00
	uart_tx_rx	38.000s	24107.157us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	7.000s	10814.494us	1	1	100.00
	uart_rx_parity_err	62.000s	39974.136us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	38.000s	24107.157us	1	1	100.00
	uart_intr	7.000s	10814.494us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	32.000s	19990.281us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	82.000s	94018.616us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	20.000s	8291.806us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	7.000s	10814.494us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	7.000s	10814.494us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	7.000s	10814.494us	1	1	100.00
perf				1	1	100.00
	uart_perf	44.000s	6510.808us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	17.000s	8487.223us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	17.000s	8487.223us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	5.000s	32838.892us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	84.000s	48810.279us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	17.000s	6802.196us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	22.000s	6011.719us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	114.000s	132053.148us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	966.000s	204804.251us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	2.000s	14.421us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	17.255us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.000s	28.990us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.000s	28.990us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	30.203us	1	1	100.00
	uart_csr_rw	1.000s	42.330us	1	1	100.00
	uart_csr_aliasing	1.000s	47.545us	1	1	100.00
	uart_same_csr_outstanding	2.000s	105.092us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	30.203us	1	1	100.00
	uart_csr_rw	1.000s	42.330us	1	1	100.00
	uart_csr_aliasing	1.000s	47.545us	1	1	100.00
	uart_same_csr_outstanding	2.000s	105.092us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	947.087us	1	1	100.00
	uart_tl_intg_err	2.000s	90.329us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	90.329us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	26.000s	2831.963us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				2 test runs
	uart_stress_all_with_rand_reset	101620710809480857959453049334422709595017342357313502856400650920524620201339	109	UVM_INFO @ 1106487020 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/429 UVM_ERROR @ 1108660472 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1138486764 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1145803032 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all	101754262059713345692295504215217883649404127406131317790251293046798432508103	171	UVM_ERROR @ 204645742129 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 204646538041 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 204647323749 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 204651731877 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				1 test run
	uart_noise_filter	71714083749138454625791358818699960587600778625379942006588867570535557361755	84	UVM_ERROR @ 25197591510 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 25197691510 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata UVM_ERROR @ 25197891510 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 25197991510 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata