Simulation Results: aes/gcm_masked

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.49 %
  • code
  • 95.61 %
  • assert
  • 98.43 %
  • func
  • 65.44 %
  • block
  • 95.78 %
  • line
  • 97.45 %
  • branch
  • 89.52 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 64.985us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 104.356us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 69.296us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 68.187us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 878.959us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 205.081us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 115.297us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 68.187us 1 1 100.00
aes_csr_aliasing 3.000s 205.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 104.356us 1 1 100.00
aes_config_error 4.000s 223.760us 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 104.356us 1 1 100.00
aes_config_error 4.000s 223.760us 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 81.636us 1 1 100.00
aes_b2b 6.000s 108.819us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 104.356us 1 1 100.00
aes_config_error 4.000s 223.760us 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
aes_alert_reset 5.000s 95.973us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 65.206us 1 1 100.00
aes_config_error 4.000s 223.760us 1 1 100.00
aes_alert_reset 5.000s 95.973us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 6.000s 95.923us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 1095.414us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 689.545us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 95.973us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 81.636us 1 1 100.00
aes_sideload 6.000s 883.799us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 115.363us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 2.000s 105.984us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 102.637us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 61.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 64.139us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 64.139us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 69.296us 1 1 100.00
aes_csr_rw 3.000s 68.187us 1 1 100.00
aes_csr_aliasing 3.000s 205.081us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.608us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 69.296us 1 1 100.00
aes_csr_rw 3.000s 68.187us 1 1 100.00
aes_csr_aliasing 3.000s 205.081us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 170.704us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 115.573us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 579.297us 1 1 100.00
aes_tl_intg_err 5.000s 195.340us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 5.000s 195.340us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 95.973us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 104.356us 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
aes_alert_reset 5.000s 95.973us 1 1 100.00
aes_core_fi 3.000s 185.312us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 102.637us 1 1 100.00
aes_config_error 4.000s 223.760us 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
aes_core_fi 3.000s 185.312us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.494us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 79.916us 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 81.636us 1 1 100.00
aes_sideload 6.000s 883.799us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 79.916us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 79.916us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 79.916us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 79.916us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 79.916us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 81.636us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 314.190us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
aes_ctr_fi 3.000s 128.696us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 314.190us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 314.190us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_ctr_fi 3.000s 128.696us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 314.190us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
aes_ctr_fi 3.000s 128.696us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 95.973us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
aes_ctr_fi 3.000s 128.696us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
aes_ctr_fi 3.000s 128.696us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_ctr_fi 3.000s 128.696us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 51.674us 1 1 100.00
aes_fi 5.000s 314.190us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 314.190us 0 1 0.00
aes_control_fi 3.000s 116.455us 1 1 100.00
aes_cipher_fi 2.000s 52.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 975.981us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 77293801842899167272324459768468343086752695205634253378430678763378434907374 6462
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 15473972134188481688028127143878543586388414275711603535897910014169101828877 159
UVM_INFO @ 975980640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---