Simulation Results: aes/gcm_unmasked

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.47 %
  • code
  • 90.67 %
  • assert
  • 97.94 %
  • func
  • 64.81 %
  • block
  • 90.84 %
  • line
  • 92.36 %
  • branch
  • 83.68 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 137.029us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 211.455us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 87.736us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 73.848us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 12.000s 909.256us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 88.002us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 219.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 73.848us 1 1 100.00
aes_csr_aliasing 2.000s 88.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 211.455us 1 1 100.00
aes_config_error 3.000s 116.121us 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 211.455us 1 1 100.00
aes_config_error 3.000s 116.121us 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 157.426us 1 1 100.00
aes_b2b 5.000s 116.335us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 211.455us 1 1 100.00
aes_config_error 3.000s 116.121us 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
aes_alert_reset 2.000s 151.357us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 196.972us 1 1 100.00
aes_config_error 3.000s 116.121us 1 1 100.00
aes_alert_reset 2.000s 151.357us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 610.812us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1424.818us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 151.357us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 157.426us 1 1 100.00
aes_sideload 3.000s 101.752us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 425.936us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10801.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 117.958us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 681.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 681.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 87.736us 1 1 100.00
aes_csr_rw 1.000s 73.848us 1 1 100.00
aes_csr_aliasing 2.000s 88.002us 1 1 100.00
aes_same_csr_outstanding 7.000s 131.300us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 87.736us 1 1 100.00
aes_csr_rw 1.000s 73.848us 1 1 100.00
aes_csr_aliasing 2.000s 88.002us 1 1 100.00
aes_same_csr_outstanding 7.000s 131.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 188.400us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 8.000s 825.986us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 8.000s 528.485us 1 1 100.00
aes_tl_intg_err 2.000s 189.821us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 189.821us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 151.357us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 211.455us 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
aes_alert_reset 2.000s 151.357us 1 1 100.00
aes_core_fi 3.000s 184.406us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 116.121us 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
aes_core_fi 3.000s 184.406us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 7.000s 65.957us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 181.453us 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 157.426us 1 1 100.00
aes_sideload 3.000s 101.752us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 181.453us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 181.453us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 181.453us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 181.453us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 181.453us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 157.426us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 120.007us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
aes_ctr_fi 2.000s 84.058us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 120.007us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 120.007us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_ctr_fi 2.000s 84.058us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 120.007us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
aes_ctr_fi 2.000s 84.058us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 151.357us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
aes_ctr_fi 2.000s 84.058us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
aes_ctr_fi 2.000s 84.058us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_ctr_fi 2.000s 84.058us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 120.007us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 120.007us 0 1 0.00
aes_control_fi 1.000s 86.765us 1 1 100.00
aes_cipher_fi 3.000s 86.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 8.469us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 18341401915386112270131440832252524458062258492649856512646658459113895082011 8214
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 3
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 11425327165588727414976624526699719220482738336940821369913551863616420312426 None
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 85168681049620020292264460015386210282401972263004264597066478459415100353730 153
UVM_INFO @ 8468546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---