Simulation Results: alert_handler

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.52 %
  • code
  • 92.14 %
  • assert
  • 98.29 %
  • func
  • 78.14 %
  • line
  • 99.76 %
  • branch
  • 97.88 %
  • cond
  • 90.91 %
  • toggle
  • 91.51 %
  • FSM
  • 80.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 21.970s 245.572us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.140s 121.730us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.170s 70.924us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 171.170s 5763.139us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 27.220s 257.254us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.200s 70.529us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.170s 70.924us 1 1 100.00
alert_handler_csr_aliasing 27.220s 257.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 44.030s 937.546us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 74.640s 2657.186us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2297.800s 43644.936us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.440s 3085.906us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 21.970s 245.572us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 74.110s 1378.590us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 45.950s 877.343us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 118.870s 2733.654us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 892.600s 35784.997us 1 1 100.00
alert_handler_lpg_stub_clk 3488.300s 80152.849us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2743.310s 115599.528us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.130s 802.958us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.490s 93.186us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.260s 15.060us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 30.700s 827.118us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 30.700s 827.118us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.140s 121.730us 1 1 100.00
alert_handler_csr_rw 6.170s 70.924us 1 1 100.00
alert_handler_csr_aliasing 27.220s 257.254us 1 1 100.00
alert_handler_same_csr_outstanding 49.750s 1501.412us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.140s 121.730us 1 1 100.00
alert_handler_csr_rw 6.170s 70.924us 1 1 100.00
alert_handler_csr_aliasing 27.220s 257.254us 1 1 100.00
alert_handler_same_csr_outstanding 49.750s 1501.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 209.010s 5628.850us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 209.010s 5628.850us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 209.010s 5628.850us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 209.010s 5628.850us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 688.510s 14882.577us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
alert_handler_tl_intg_err 22.760s 188.201us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 22.760s 188.201us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 209.010s 5628.850us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 21.970s 245.572us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 21.970s 245.572us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 21.970s 245.572us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 21.970s 245.572us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.440s 3085.906us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 892.600s 35784.997us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.440s 3085.906us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2297.800s 43644.936us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2297.800s 43644.936us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 18.620s 474.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 10.570s 275.118us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 46150986899082088606463080687786694700777273817341991707434423554560842900983 105
UVM_INFO @ 2733653903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 100971070386809483207325160049184152947113606058867272953602446530124456489418 208
UVM_INFO @ 802957738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 25719546220674185438088119622303890764147458260081933156622432814265913660553 88
UVM_INFO @ 275118226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---