| V1 |
|
27.27% |
| V2 |
|
36.41% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
40.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_uart_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 13.371s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx | 13.371s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_rand_baudrate | 0 | 1 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 32.237s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 26.463s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_gpio_out | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 485.550s | 285.561us | 1 | 1 | 100.00 | |
| chip_sw_gpio_in | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 485.550s | 285.561us | 1 | 1 | 100.00 | |
| chip_sw_gpio_irq | 1 | 1 | 100.00 | |||
| chip_sw_gpio | 485.550s | 285.561us | 1 | 1 | 100.00 | |
| chip_sw_example_tests | 1 | 4 | 25.00 | |||
| chip_sw_example_rom | 57.050s | 10.260us | 0 | 1 | 0.00 | |
| chip_sw_example_manufacturer | 15.321s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_example_concurrency | 298.250s | 168.859us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest_signed | 12.874s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 10.550s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 14.650s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 14.650s | 0.000us | 0 | 1 | 0.00 | |
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 13.150s | 12.836us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_spi_device_flash_mode | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 82.979s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_pass_through | 1 | 1 | 100.00 | |||
| chip_sw_spi_device_pass_through | 3057.770s | 4805.231us | 1 | 1 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 360.850s | 245.502us | 0 | 1 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 1 | 0.00 | |||
| chip_sw_spi_device_tpm | 13.551s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 13.411s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 12.782s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 12.971s | 0.000us | 0 | 1 | 0.00 | |
| chip_pin_mux | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 3.130s | 0.000us | 0 | 1 | 0.00 | |
| chip_padctrl_attributes | 0 | 1 | 0.00 | |||
| chip_padctrl_attributes | 3.130s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_wake | 17.505s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 1 | 0.00 | |||
| chip_sw_sleep_pin_retention | 19.977s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 12.158s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 1 | 0.00 | |||
| chip_sw_data_integrity_escalation | 12.158s | 0.000us | 0 | 1 | 0.00 | |
| chip_jtag_csr_rw | 0 | 1 | 0.00 | |||
| chip_jtag_csr_rw | 155.210s | 132.349us | 0 | 1 | 0.00 | |
| chip_jtag_mem_access | 0 | 1 | 0.00 | |||
| chip_jtag_mem_access | 163.980s | 131.576us | 0 | 1 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 494.890s | 310.147us | 1 | 1 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.946s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 11.932s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 1 | 0.00 | |||
| chip_rv_dm_lc_disabled | 224.290s | 259.812us | 0 | 1 | 0.00 | |
| chip_sw_timer | 1 | 1 | 100.00 | |||
| chip_sw_rv_timer_irq | 360.760s | 266.830us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 689.990s | 574.386us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_irq | 689.990s | 574.386us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 615.540s | 386.593us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 347.750s | 182.704us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 347.750s | 182.704us | 0 | 1 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 1 | 1 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 554.230s | 2310.456us | 1 | 1 | 100.00 | |
| chip_sw_plic_sw_irq | 1 | 1 | 100.00 | |||
| chip_sw_plic_sw_irq | 274.680s | 164.296us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 4 | 4 | 100.00 | |||
| chip_sw_otbn_randomness | 393.070s | 245.133us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 255.140s | 165.920us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_idle | 275.210s | 178.188us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 275.310s | 163.958us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_off_trans | 0 | 4 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 307.340s | 185.392us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 264.730s | 185.376us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 282.020s | 185.440us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 273.980s | 185.424us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 1 | 6 | 16.67 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 57.910s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 70.680s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 54.520s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 62.520s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.608s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 224.850s | 161.273us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_extended_range | 1 | 7 | 14.29 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 589.620s | 1963.011us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 57.450s | 10.160us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 55.040s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 53.990s | 10.200us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 59.410s | 10.220us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 50.750s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 59.950s | 10.360us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 47.368s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 13.630s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 1 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 12.859s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1557.400s | 943.617us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 1 | 1 | 100.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 493.230s | 509.929us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_sleep_all_reset_reqs | 0 | 1 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 347.750s | 182.704us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 13.046s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_power_glitch_reset | 1 | 1 | 100.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 493.230s | 509.929us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 15.580s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 17.630s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 21.655s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 12.996s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 1 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 16.063s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1557.400s | 943.617us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 1 | 1 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 494.890s | 310.147us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 625.380s | 412.160us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 402.570s | 305.456us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_alert_info | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 466.700s | 331.160us | 0 | 1 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 1 | 1 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 268.380s | 163.760us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1557.400s | 943.617us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_test | 33.290s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 41.647s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1557.400s | 943.617us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_entropy | 21.750s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 466.700s | 331.160us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 1 | 1 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 326.120s | 248.031us | 1 | 1 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 122.730s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 116.235s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 111.317s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 116.180s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 116.864s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 1 | 0.00 | |||
| chip_sw_alert_handler_escalation | 41.647s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 16.725s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_broadcast | 2 | 9 | 22.22 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 14.044s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 14.689s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 12.355s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 14.048s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 1212.180s | 1294.113us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 14.235s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 835.940s | 964.758us | 1 | 1 | 100.00 | |
| chip_rv_dm_lc_disabled | 224.290s | 259.812us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 242.450s | 173.121us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 70.680s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 1 | 2 | 50.00 | |||
| chip_sw_aes_enc | 242.450s | 173.121us | 1 | 1 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 70.680s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_aes_entropy | 1 | 1 | 100.00 | |||
| chip_sw_aes_entropy | 277.950s | 164.505us | 1 | 1 | 100.00 | |
| chip_sw_aes_idle | 1 | 1 | 100.00 | |||
| chip_sw_aes_idle | 255.140s | 165.920us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc | 1 | 2 | 50.00 | |||
| chip_sw_hmac_enc | 284.420s | 173.800us | 1 | 1 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 54.520s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_hmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_hmac_enc_idle | 275.210s | 178.188us | 1 | 1 | 100.00 | |
| chip_sw_kmac_enc | 2 | 3 | 66.67 | |||
| chip_sw_kmac_mode_cshake | 281.470s | 167.450us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac | 340.150s | 188.915us | 1 | 1 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 62.520s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_lc | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 1 | 0.00 | |||
| chip_sw_kmac_app_rom | 19.198s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_kmac_entropy | 1 | 1 | 100.00 | |||
| chip_sw_kmac_entropy | 366.490s | 195.133us | 1 | 1 | 100.00 | |
| chip_sw_kmac_idle | 1 | 1 | 100.00 | |||
| chip_sw_kmac_idle | 275.310s | 163.958us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_csrng | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 2109.280s | 2223.994us | 1 | 1 | 100.00 | |
| chip_sw_csrng_edn_cmd | 1 | 1 | 100.00 | |||
| chip_sw_entropy_src_csrng | 2109.280s | 2223.994us | 1 | 1 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 1 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 15.338s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 1 | 1 | 100.00 | |||
| chip_sw_csrng_kat_test | 321.840s | 176.031us | 1 | 1 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1 | 1 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 1918.740s | 881.147us | 1 | 1 | 100.00 | |
| chip_sw_otbn_op | 1 | 2 | 50.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 3571.090s | 1504.369us | 1 | 1 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 57.910s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 393.070s | 245.133us | 1 | 1 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 393.070s | 245.133us | 1 | 1 | 100.00 | |
| chip_sw_otbn_idle | 1 | 1 | 100.00 | |||
| chip_sw_otbn_randomness | 393.070s | 245.133us | 1 | 1 | 100.00 | |
| chip_sw_otbn_mem_scramble | 1 | 1 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 514.900s | 280.496us | 1 | 1 | 100.00 | |
| chip_sw_rom_access | 1 | 1 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 1212.180s | 1294.113us | 1 | 1 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 1 | 1 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 1212.180s | 1294.113us | 1 | 1 | 100.00 | |
| chip_sw_sram_scrambled_access | 1 | 2 | 50.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 500.610s | 350.038us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.608s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_execution | 0 | 1 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 14.235s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 2 | 0.00 | |||
| chip_sw_all_escalation_resets | 1557.400s | 943.617us | 0 | 1 | 0.00 | |
| chip_sw_data_integrity_escalation | 12.158s | 0.000us | 0 | 1 | 0.00 | |
| chip_otp_ctrl_init | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_keys | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 514.900s | 280.496us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 500.610s | 350.038us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 297.610s | 172.226us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 514.900s | 280.496us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 500.610s | 350.038us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 297.610s | 172.226us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_program | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 16.860s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg | 16.725s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 1 | 6 | 16.67 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 14.044s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 14.689s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 12.355s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 14.048s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_transition | 18.701s | 0.000us | 0 | 1 | 0.00 | |
| chip_prim_tl_access | 835.940s | 964.758us | 1 | 1 | 100.00 | |
| chip_sw_otp_prim_tl_access | 1 | 1 | 100.00 | |||
| chip_prim_tl_access | 835.940s | 964.758us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_nvm_cnt | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_nvm_cnt | 12.230s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_sw_parts | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_sw_parts | 12.162s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 1 | 0.00 | |||
| chip_sw_ast_clk_outputs | 47.368s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 1 | 6 | 16.67 | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 57.910s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 70.680s | 10.320us | 0 | 1 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 54.520s | 10.120us | 0 | 1 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 62.520s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.608s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_clkmgr_jitter | 224.850s | 161.273us | 1 | 1 | 100.00 | |
| chip_sw_soc_proxy_external_reset_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 209.570s | 156.224us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_irqs | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_smoketest | 209.570s | 156.224us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_external_wakeup_requests | 0 | 1 | 0.00 | |||
| chip_sw_soc_proxy_external_wakeup | 225.440s | 157.858us | 0 | 1 | 0.00 | |
| chip_sw_soc_proxy_gpios | 1 | 1 | 100.00 | |||
| chip_sw_soc_proxy_gpios | 234.430s | 172.119us | 1 | 1 | 100.00 | |
| chip_sw_nmi_irq | 0 | 1 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 573.180s | 269.250us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 429.870s | 213.993us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 310.250s | 179.892us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 297.610s | 172.226us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 625.380s | 412.160us | 0 | 1 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 1 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 625.380s | 412.160us | 0 | 1 | 0.00 | |
| chip_sw_smoketest | 14 | 14 | 100.00 | |||
| chip_sw_aes_smoketest | 294.880s | 173.205us | 1 | 1 | 100.00 | |
| chip_sw_aon_timer_smoketest | 288.330s | 182.340us | 1 | 1 | 100.00 | |
| chip_sw_clkmgr_smoketest | 239.960s | 162.154us | 1 | 1 | 100.00 | |
| chip_sw_csrng_smoketest | 272.110s | 164.347us | 1 | 1 | 100.00 | |
| chip_sw_gpio_smoketest | 306.840s | 184.606us | 1 | 1 | 100.00 | |
| chip_sw_hmac_smoketest | 343.750s | 195.024us | 1 | 1 | 100.00 | |
| chip_sw_kmac_smoketest | 334.000s | 185.534us | 1 | 1 | 100.00 | |
| chip_sw_otbn_smoketest | 371.620s | 220.999us | 1 | 1 | 100.00 | |
| chip_sw_otp_ctrl_smoketest | 256.040s | 165.885us | 1 | 1 | 100.00 | |
| chip_sw_rv_plic_smoketest | 219.360s | 164.109us | 1 | 1 | 100.00 | |
| chip_sw_rv_timer_smoketest | 371.700s | 266.882us | 1 | 1 | 100.00 | |
| chip_sw_rstmgr_smoketest | 285.600s | 161.121us | 1 | 1 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 302.790s | 164.608us | 1 | 1 | 100.00 | |
| chip_sw_uart_smoketest | 291.140s | 175.207us | 1 | 1 | 100.00 | |
| chip_sw_rom_functests | 0 | 1 | 0.00 | |||
| rom_keymgr_dpe_functest | 13.765s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_signed | 0 | 1 | 0.00 | |||
| chip_sw_uart_smoketest_signed | 12.874s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_boot | 0 | 1 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 82.979s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_secure_boot | 0 | 1 | 0.00 | |||
| base_rom_e2e_smoke | 10.736s | 0.000us | 0 | 1 | 0.00 | |
| chip_lc_scrap | 4 | 4 | 100.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 323.120s | 227.417us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 237.520s | 225.974us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 241.140s | 214.673us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 255.610s | 230.159us | 1 | 1 | 100.00 | |
| chip_lc_test_locked | 0 | 2 | 0.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 13.974s | 0.000us | 0 | 1 | 0.00 | |
| chip_rv_dm_lc_disabled | 224.290s | 259.812us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 5 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 113.621s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 93.440s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 12.878s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 86.264s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 13.974s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 2 | 3 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 671.320s | 645.345us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 737.830s | 648.337us | 1 | 1 | 100.00 | |
| rom_volatile_raw_unlock | 35.519s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 1 | 0.00 | |||
| rom_raw_unlock | 36.351s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 1 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 55.990s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 1 | 0.00 | |||
| chip_sw_inject_scramble_seed | 26.322s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 179.980s | 117.992us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| chip_tl_errors | 179.980s | 117.992us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 14.650s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 12.050s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 2 | 0.00 | |||
| chip_csr_aliasing | 14.650s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 12.050s | 0.000us | 0 | 1 | 0.00 | |
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 47.520s | 28.121us | 1 | 1 | 100.00 | |
| xbar_random_delay | 6 | 6 | 100.00 | |||
| xbar_smoke_zero_delays | 12.470s | 12.152us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 426.390s | 2567.562us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 490.990s | 2196.952us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 44.250s | 25.885us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 1059.450s | 6725.684us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 1643.930s | 6840.138us | 1 | 1 | 100.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 166.640s | 170.211us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 32.070s | 23.395us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 28.270s | 18.744us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 32.070s | 23.395us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 157.260s | 271.005us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 2791.610s | 14040.862us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 217.520s | 406.661us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 1182.820s | 2384.093us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 315.880s | 212.723us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 1252.710s | 731.411us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 183.160s | 156.752us | 1 | 1 | 100.00 | |
| rom_e2e_smoke | 0 | 1 | 0.00 | |||
| rom_e2e_smoke | 11.807s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_output | 26.742s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 1 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 17.435s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 66.167s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 15.181s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 15.539s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 12.716s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 12.257s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 67.542s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 12.648s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 13.548s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 13.676s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 14.836s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 179.511s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 14.167s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 17.252s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 14.626s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 13.442s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 85.930s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 28.669s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 17.827s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 23.122s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 18.217s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 165.373s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 26.943s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 18.043s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 26.947s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 18.875s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 52.888s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 18.703s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 20.257s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 19.053s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 19.988s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 5 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 83.416s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_dev | 13.095s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod | 13.445s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_prod_end | 15.594s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init_rma | 14.460s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_dpe_init | 0 | 3 | 0.00 | |||
| rom_e2e_keymgr_dpe_init_rom_ext_meas | 29.604s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_dpe_init_rom_ext_no_meas | 12.703s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas | 13.246s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_static_critical | 0 | 1 | 0.00 | |||
| rom_e2e_static_critical | 13.019s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 1 | 1 | 100.00 | |||
| chip_sw_aes_masking_off | 304.790s | 196.067us | 1 | 1 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 1 | 1 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 207.490s | 132.500us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 22.451s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 24.273s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 16.308s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 1 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 20.453s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_plic_alerts | 0 | 1 | 0.00 | |||
| chip_sw_all_escalation_resets | 1557.400s | 943.617us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 20.419s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 287.130s | 176.856us | 0 | 1 | 0.00 | |
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 12.816s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 1 | 0.00 | |||
| chip_sw_power_virus | 129.001s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 22.451s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 24.273s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 16.308s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 15.204s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 41.145s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 17.396s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 1 | 0.00 | |||
| rom_e2e_self_hash | 61.852s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 8 | 20 | 40.00 | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 56.870s | 10.240us | 0 | 1 | 0.00 | |
| chip_sw_aes_gcm | 353.570s | 203.547us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_kat_test | 277.760s | 163.541us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 257.020s | 161.289us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_0 | 566.960s | 327.661us | 1 | 1 | 100.00 | |
| chip_plic_all_irqs_10 | 510.890s | 300.673us | 1 | 1 | 100.00 | |
| chip_sw_dma_inline_hashing | 342.380s | 210.434us | 1 | 1 | 100.00 | |
| chip_sw_dma_abort | 371.150s | 208.735us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 37.988s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 37.501s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_otbn | 15.749s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_dev_sw | 19.619s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_otbn | 11.452s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_sw | 11.864s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 15.330s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_prod_end_sw | 13.181s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_otbn | 13.715s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_mod_exp_rma_sw | 12.841s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_entropy_src_smoketest | 346.010s | 190.878us | 1 | 1 | 100.00 | |
| chip_sw_mbx_smoketest | 604.090s | 398.716us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 119 test runs | |||
| chip_sw_example_manufacturer | 29207090729925952138871439364099911535102454991890625633666730344272317507665 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.651s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_data_integrity_escalation | 26516418802370661454684288506638067922066947591631306463310951108370795586763 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.373s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_wake | 111520469010478307228491080103047642510787665993376364523270418513196484283198 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.958s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sleep_pin_retention | 79259487236147679317836743874772424875805631195457338450415434042507409080905 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.013s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx | 115756557936386697912420647978781134826483849063971744195645604940480191432068 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.413s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_bootstrap | 86466609095737569802715882625401372065211462860570639092788315432398696388835 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 13.419s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_inject_scramble_seed | 8057371357554331099325572776048837654245056585774099239514010531883089689082 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.542s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_exit_test_unlocked_bootstrap | 90334418474717672720891516042534060330077340804993002019959233333843802533657 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.873s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_rand_baudrate | 58787693361785554896193666596761960255399937572366990123535703269015657135043 | None |
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.779s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_tx_rx_alt_clk_freq | 87741480124734407826312426897460951968654637953095575215503920218933601709375 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.538s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_host_tx_rx | 112864723475056458545008504266059924135311440094469958634568184376304564713153 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.376s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_i2c_device_tx_rx | 6002865982222091399905972928534668589620720119630348317630155601286878029458 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.420s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_device_tpm | 87768568782757231130067811170829589299251266563566401115144000970649913863555 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.370s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_spi_host_tx_rx | 56290868432064806515599784848700341907078802696748263211140785224568062114675 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.382s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_otp_hw_cfg | 106178683464942830568590097480337751764111958992533360469147114440649564013318 | None |
Another command (pid=1181794) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=1181955) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=1184199) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 64474765998585873912037895944545178930715504216773659207605116932989322466076 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.387s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_dev | 46422771180118443274227466060195107721322426074454408530086783744683631130000 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.729s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_prod | 49286342623728856913499873369941562895493255220120393768914879984379471417745 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.409s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 74722172843515912561676288344145315904017714101923276242889577372671139879773 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.380s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_vendor_test_csr_access | 5679227245908615932058705559448126905482918452930377889741582177903735761314 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.096s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_nvm_cnt | 108492907749561660785537941014220753355748936118584567381880235409297047613646 | None |
---- STDERR ----
Another command (pid=402349) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=523639) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_otp_ctrl_sw_parts | 84783552653190975412811703127049670569514193998786735735825795493687167094505 | None |
---- STDERR ----
Another command (pid=525720) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=526638) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_transition | 109252709672903124960977315095431849952311564735418952113505328755363580235523 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.967s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_dev | 12901697295866398259355842953986893506607928453369982067857762782720401505272 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 16.896s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prod | 23726640865670636960787032218146760117873342531084611836596467171852988658969 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.337s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_prodend | 35502830600008307093273584968327463899331632379922171034887464087365491723139 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.387s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_rma | 81762122287710281602187866022415334703164633825742428228249557469191194786426 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.468s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_walkthrough_testunlocks | 102042443533239744917578641790289783746077417342344680316142097741946712881781 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.601s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_main_power_glitch_reset | 93625004103216064905712097536354326146200904145502890428672744612325186432895 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.731s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 108673040100695121027614448765927974897989086253379896245172119860320545312513 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.393s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 54465555683877298425838013037401777503524100643522071066000499034263795743896 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.473s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 10136499177702489378477190588121026684670870364203372836612278161594392592821 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.852s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_disabled | 1669540622237654807595976598993286796637988586316728777108890973989769853664 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.582s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_wdog_reset | 17223300780422062798939129573722843917155455701415218355200699446513867929 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.390s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_test | 70438818230741046970679533743668460190841378897948519680390053821607802867278 | None |
Another command (pid=672163) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_escalation | 107232677553016609951070573402045471714848123221994986648149470327505167195233 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 26.690s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 80956698590119970765345694861261428202301756376358325205798531622641985011785 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 16.995s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 82852557627014191091044436903980656203569407703617525992152529184368005890441 | None |
Another command (pid=399294) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=523639) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=526638) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_sleep_mode_pings | 69228262216585459455991539397956045898931078058584102713080116196915552827622 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.327s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_clkoff | 80620539217978596323966846438446641510496459077318394805031591714082905462102 | None |
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.321s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_lpg_reset_toggle | 53975567323788350562484560613297185603380973854459962708512660095743473768531 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.246s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_alert_handler_entropy | 95443573071232939411262535172298396345556095187650046312426225546427313609187 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.873s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 62232354560072032987306659659638042399559503926327321920722341781298344521980 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.034s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_kmac_app_rom | 98165257728337782741017033599186355635462111414583369837461554040022774147888 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the build_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 16360173291040292516050694058516351694092925352959194335600137598103058776761 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_sram_ctrl_execution_main | 83641716663841555334293467636111783202853696362140292813376930733300257015452 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.561s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_coremark | 105133650944785900135486518934834102769219390322744951937631457983101499988901 | None |
Another command (pid=521886) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_reset_frequency | 10749610601272016480571538577854405460455347380208471727231296054579493033386 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.445s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_clkmgr_sleep_frequency | 101988970216678392363516759301579566954398987929967236430729634959162669106837 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.378s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_ast_clk_outputs | 42504305240835465812818814892358334236774997034138870210305526614691509031275 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.449s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_lc_ctrl_program_error | 107370768811045093955410656401549586169385078451345987097352914856289261328745 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.898s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 97398460502120675535580592928830658010608991123432105350379511313215655126570 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_wakeup | 64915477278563029270707838733483518611476357871734887246679676028582104123496 | None |
---- STDERR ----
Another command (pid=1319745) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_rv_dm_access_after_escalation_reset | 23731332368774633275766218182129486421801038737511093006970031746375451911012 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.124s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_power_virus | 48650061065620326687213597926668896435969914293553942930510094811591593213272 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.634s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| base_rom_e2e_smoke | 45368436272023873163392217382801952282634415982378341888100461572695253619780 | None |
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 329, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 261, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_smoke | 82996830312979243355512522559238997431735443842949568948521758284516122010300 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_exception_c | 101497066785091126538100180878944029332009812481692909176684223188805627920226 | None |
---- STDERR ----
Another command (pid=580282) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=576979) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_shutdown_output | 103359336878803739883811207166525443304374069847748757884790343563145715241963 | None |
Another command (pid=594956) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=581168) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=596482) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 9537598554297218321778594510645360807023733953818206857163483377180089646020 | None |
Another command (pid=316803) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=368190) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=355102) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 60448906702466052534568160077335971253504544453029084836154489969045353775981 | None |
Another command (pid=550607) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=553126) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=547083) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 78403598601459224056093780514120079499138526638415345296238316776299795302403 | None |
Another command (pid=550828) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=554907) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=556951) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 45099216665401717645081880726834176722660799698724824257149486376687474374665 | None |
---- STDERR ----
Another command (pid=547953) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 47168540877171812925955042326633649325194967041066964198992117487907461152832 | None |
---- STDERR ----
Another command (pid=547083) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=553709) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 16993924867488966771717534457359959894286583726814149049178747128937263033062 | None |
Another command (pid=368190) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=379221) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=317995) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 21759630866722940912512446016649436740411416408083747315423675842757720914180 | None |
---- STDERR ----
Another command (pid=539945) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 7427928939646058065740959350173185125006574790240389431831812351626055083909 | None |
Another command (pid=537722) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=532694) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=544033) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 46578759162743331313902358177089003304105792334535248158286898119594613759140 | None |
---- STDERR ----
Another command (pid=544033) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=546269) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 8161604587309465607668454594271727755186545236873525636261205643583140036545 | None |
Another command (pid=547953) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=550607) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=553126) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 103329836209586535432933645355285947423017449790815468801499248267557522817822 | None |
Another command (pid=402763) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=478325) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=434470) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 58043838397200265148698279144877189299100122598032056693497048340459276186157 | None |
---- STDERR ----
Another command (pid=535653) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 3636417438441536476350256550025412624606168343295160326105711669489072550835 | None |
Another command (pid=542719) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=537722) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=532694) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 103165413082212715418299353544603719795208571293994423119700475419794623769922 | None |
---- STDERR ----
Another command (pid=542255) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 28319595061035066374104092531495292672686430386127326682161802920980187534239 | None |
---- STDERR ----
Another command (pid=539694) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 41586741706844106911043208496580712440620165660063159032648610384888741763636 | None |
Another command (pid=379760) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=380541) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=343246) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 72259437818670779722575971034448534087007450652447869136601798551543325122248 | None |
Another command (pid=606233) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=600026) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=601005) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 56376146498163163013145828166721595243922090669279207604067524563035978507601 | None |
---- STDERR ----
Another command (pid=565891) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=585000) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 30418041912195522597927066820887482711015457464431863738869378187667708949685 | None |
Another command (pid=595421) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=598425) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=594956) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 64111469562741468236352789400190351091297755538860231349827826694881353687585 | None |
---- STDERR ----
Another command (pid=561934) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=591100) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 100332978528498266116399311010778627192866369030732948727360365861946857146767 | None |
Another command (pid=502962) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=400583) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=505886) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 103404638950422154766267667237984001299681366816036888973892979684719916253286 | None |
Another command (pid=615857) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=613241) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=620870) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 3296933359516008505051980411902946468435281640260498901157672687098120845768 | None |
Another command (pid=596482) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=603450) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=596035) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 14214543522910266662897961204761483401842616106781809164792394864486539878173 | None |
Another command (pid=613241) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=620870) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=616012) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 68173184942297145117617956268128247706684484596004407197500199557749713107041 | None |
Another command (pid=606233) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=600026) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=601005) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 90410804259547746871977712779542268795578931283932723541479874137621066609999 | None |
---- STDERR ----
Another command (pid=376237) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=383355) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 66650625754800078160050487553569531125058278451810672451188801202239769821549 | None |
Another command (pid=601005) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=594472) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=610722) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 96912960617385599284215281428442388137564511845815400991373319900195914090100 | None |
Another command (pid=620870) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=616012) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=623605) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 28221080497113589294499166414692959671987549247747868414604106621159048717496 | None |
---- STDERR ----
Another command (pid=620870) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=616012) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 26756522525069707952312456339438924767750279010331462628149768870773086450070 | None |
Another command (pid=616012) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=619431) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=623621) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 15559178961872252549418515857337276907291138139635548680766294803309250103362 | None |
Another command (pid=334122) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=368190) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=379221) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 44924421125540679234856091259604641476735405056228185378057848160447604282435 | None |
Waiting for it to complete...
Another command (pid=529092) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 60991872047973464741240582819626759752522475917608550634428897138046347718706 | None |
Another command (pid=529092) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=530577) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=530568) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 21725538497472234930312034083430527694904960594752555433931019421102082067830 | None |
Another command (pid=523252) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=534817) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=537357) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 112671605247810230407457222395777369106868174076556992621148560538963886688586 | None |
Another command (pid=526177) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=523252) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=534817) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 39540218534738657926620864593176960895647601194179330444678509702437794357617 | None |
Another command (pid=582567) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=583522) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=565891) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_dev | 38161259827504738252927293027015759187290687280397766094365150994952840145634 | None |
Another command (pid=576979) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=582567) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=583522) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_debug_rma | 28892541762442992943392783750432265629178045647816767093652198490709702099615 | None |
Another command (pid=567029) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=568936) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=569641) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 53980144377186714651853282029362278258479723381100145442113926808428437465159 | None |
Another command (pid=488265) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=480399) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=497744) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_dev | 24848949101679023645450705045631483947097083603902305917074828079925398140569 | None |
Another command (pid=429675) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=487370) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=483596) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_jtag_inject_rma | 42330855859854944800017996553597845591794642231513413856644006717977605844547 | None |
Another command (pid=434470) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=480797) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=402689) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_static_critical | 71447766925310086801588986898584030838841531120764313707154087309928420920112 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_dpe_init_rom_ext_meas | 36095337956996559949823287112798980079515533271201598961198259877975878220302 | None |
Another command (pid=598425) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=594956) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=596482) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': target 'rom_e2e_keymgr_dpe_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': target 'rom_e2e_keymgr_dpe_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_dpe_init_rom_ext_no_meas | 86774245349982772739151503250711463910548099947025471982916285308473897825108 | None |
---- STDERR ----
Another command (pid=569434) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': target 'rom_e2e_keymgr_dpe_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': target 'rom_e2e_keymgr_dpe_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas | 18622354616781851946856659042740938223960926143754329184772139709551202555550 | None |
---- STDERR ----
Another command (pid=567029) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=568936) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': target 'rom_e2e_keymgr_dpe_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_dpe_init_test_sim_dv': target 'rom_e2e_keymgr_dpe_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 96566961589016975885354692899707465672693185686594521126219280990887971003480 | None |
---- STDERR ----
Another command (pid=312330) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 92634664032613892146690094914957582312571442985968687115688992630094417505742 | None |
Another command (pid=352034) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=316803) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=357861) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_otbn | 40371567331647890194678387851735382425091526480114806373248848705709757711776 | None |
---- STDERR ----
Another command (pid=612711) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=596337) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_dev_sw | 15717091505941157754213015132485522843176303712955557090266628279405410799838 | None |
Another command (pid=623621) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=615377) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=627900) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_otbn | 77310684455135483319513151062997282887977200925227764341241654902768365384595 | None |
---- STDERR ----
Another command (pid=616012) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_sw | 469337449029266399941594577860268647445584361160938104446995602281726763199 | None |
---- STDERR ----
Another command (pid=623621) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 1671582604170712503883540007384136482217473894600073559909409627842680312243 | None |
Another command (pid=613241) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=620870) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=616012) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_prod_end_sw | 76387345146895378214003128349520279148794323762433815383404423559919290352560 | None |
---- STDERR ----
Another command (pid=623621) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_otbn | 91924052134164711853461222137090952693409325153012319778399459660428084575747 | None |
Another command (pid=627900) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=616543) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=629874) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_sigverify_mod_exp_rma_sw | 107997180833429079819333922188361417999341186471701532902271568272726685775104 | None |
---- STDERR ----
Another command (pid=629874) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 8342755994103815392509492598469116908702552966014413462186242550847601473810 | None |
Another command (pid=312330) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=352034) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=316803) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 46860912811057696843716733230817711187071860181079708240702535010545876171337 | None |
Another command (pid=352034) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=316803) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=334122) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 47722850807658958752411152116318514160075707732186518275309409466349413650943 | None |
---- STDERR ----
Another command (pid=357861) is running. Waiting for it to complete on the server (server_pid=204728)...
Another command (pid=356769) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_uart_smoketest_signed | 94511652360172673259426228656914340012580537420776849039295824747139818561134 | None |
---- STDERR ----
Another command (pid=529092) is running. Waiting for it to complete on the server (server_pid=204728)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_keymgr_dpe_functest | 114213375165820365659852566721125057989056542395754124172096127284941776355700 | None |
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_dpe_functest_sim_dv (ca9a07) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.381s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_FATAL @ * us: (dv_utils_pkg.sv:253) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" | 10 test runs | |||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 58308214372713248083206809493096205202255044471349997656853513246478080991613 | 319 |
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en | 63114898171417199578400666293388072315240356468163039387235135967499365397526 | 319 |
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en | 36989145725974002408025464127933551242983407933535699867695308101450192117588 | 324 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en | 20375615833698284228818189390446428457738033306915210976578607204655500895967 | 324 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 9868649000204086419488610859349944002451058824432599441854107921974983875327 | 319 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aes_enc_jitter_en_reduced_freq | 5404420722457178068081985965461549075325274496532955072027336091054544879209 | 319 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_hmac_enc_jitter_en_reduced_freq | 47927988341029302186029381882642812682492380700321964244097684048578357018260 | 324 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 40685673242568101259327068488939123065458708026521779370165918230980423800020 | 319 |
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9170029054456105686876650637901110753587757025089926940928233738614276685515 | 319 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_edn_concurrency_reduced_freq | 79463171192380251312894537448630182337392145409972447220504318116356319178774 | 319 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!rstreqs[*]) && (reset_cause != HwReq))' | 5 test runs | |||
| chip_sw_rstmgr_cpu_info | 77715784855442919966902945224170199672403795287233848951444287680322110529846 | 353 |
UVM_ERROR @ 412.160000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.160000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_aes_trans | 109976040515541344607700742671423610907309506801579046720711646314348088972834 | 335 |
UVM_ERROR @ 185.392000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.392000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_hmac_trans | 43859747431183734303645530691079372433337047801786530904097664670982942236752 | 335 |
UVM_ERROR @ 185.376000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.376000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_kmac_trans | 45788084242599746040361120542146045847616060348713997936888380915507439452408 | 335 |
UVM_ERROR @ 185.440000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_off_otbn_trans | 20932782536117317148083690752322251266512778152455858036906058966048525313765 | 335 |
UVM_ERROR @ 185.424000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.424000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:784) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode | 3 test runs | |||
| chip_csr_bit_bash | 61912313726210754683186847843531739927865064213357744235301909288659887518330 | 143 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_csr_aliasing | 57440815561220034812021708342968104140521018027010620262754990099597219195952 | 143 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_same_csr_outstanding | 111178090795201207806854529501875497732464594417697815934857255057286152650025 | 143 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (jtag_riscv_driver.sv:221) [jtag_riscv_agent_pkg] Check failed sbcs_val[SbAccess32] == * (* [*] vs * [*]) expect SBA width to be * bits! | 2 test runs | |||
| chip_jtag_csr_rw | 53746936517846311731506480224329510664237134857470113572518269917358181066347 | 5963 |
UVM_INFO @ 132.349000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| chip_jtag_mem_access | 83479508766151576332611388866196138526474972997484904972731563304958191662527 | 5963 |
UVM_INFO @ 131.576000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (mem_bkdr_util.sv:784) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_example_rom | 6837081926235313034372794605742410625580284376902974350590157907066594226059 | 296 |
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | 1 test run | |||
| chip_sw_all_escalation_resets | 42837745154786005239801892116742690498568752255651778420136086240102544571096 | 359 |
UVM_INFO @ 943.617000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path | 1 test run | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 46302122421447700014990534895257864290649100666943172066560650663676685973362 | 320 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 1 test run | |||
| chip_sw_spi_device_pass_through_collision | 115471644303536659839301061625580267881587742002260697670401046219225123244136 | 341 |
UVM_INFO @ 245.502000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 1 test run | |||
| chip_sw_otp_ctrl_escalation | 42909746475160507203919689308923705531097783921774638695964539892354173216665 | 335 |
UVM_ERROR @ 176.856000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.856000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size | 1 test run | |||
| chip_sw_rstmgr_alert_info | 17162039360228466539803903183362003949240361271690028524190635710358220552598 | 349 |
UVM_INFO @ 331.160000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! | 1 test run | |||
| chip_sw_soc_proxy_smoketest | 1409508384000101930031201429359357450328556087887548487167506143017103804242 | 328 |
UVM_INFO @ 156.224000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * | 1 test run | |||
| chip_sw_soc_proxy_external_wakeup | 42452185553421164319178174245507896738606303338336183117031087323458043333279 | 326 |
UVM_INFO @ 157.858000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec | 1 test run | |||
| chip_sw_aon_timer_irq | 3633225492842794079705621066617748339719405785159052356346275183312846600833 | 327 |
UVM_INFO @ 574.386000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds | 1 test run | |||
| chip_sw_aon_timer_wdog_bite_reset | 64521596626862614239961489635501606979257369097040168245277321985324287864826 | 328 |
UVM_INFO @ 182.704000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired | 1 test run | |||
| chip_sw_rv_core_ibex_nmi_irq | 93346213040452021324711147714293421743131919647336195883621238262665151277020 | 329 |
UVM_INFO @ 269.250000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (cip_base_scoreboard.sv:711) scoreboard [scoreboard] On interface chip_soc_dbg_reg_block, item had unexpected d_error value(predicted *, but saw *). | 1 test run | |||
| chip_tl_errors | 57825416609270733501650281296690546020703517759383443507158503598145154364562 | 238 |
TL item was: req: (cip_tl_seq_item@31386) { a_addr: 'h2214 a_data: 'h7f156532 a_mask: 'h0 a_size: 'h2 a_param: 'h0 a_source: 'hfd a_opcode: 'h1 a_user: 'h244d0 d_param: 'h0 d_source: 'hfd d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"} .
UVM_INFO @ 117.992000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| chip_rv_dm_lc_disabled | 76338129526964457108839131768613216585559900926446312547653913250930475503827 | 232 |
UVM_INFO @ 259.812000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| Error-[CNST-CIF] Constraints inconsistency failure | 1 test run | |||
| chip_padctrl_attributes | 109233355385339845261046677662469714569105331437634296905407954925890888969230 | 288 |
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
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| UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== | 1 test run | |||
| chip_sw_dma_abort | 77586299327579479372477477975049983819597724540862679628844100364657572148491 | 360 |
UVM_INFO @ 208.735000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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