Simulation Results: clkmgr

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.95 %
  • code
  • 69.82 %
  • assert
  • 89.67 %
  • func
  • 56.37 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.45 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.100s 28.320us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.090s 35.754us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.790s 1.912us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.750s 2.008us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.350s 75.914us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
clkmgr_csr_aliasing 0.750s 2.008us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.050s 13.404us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.280s 24.443us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.850s 23.003us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.100s 28.320us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.810s 8.275us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.700s 2.511us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.810s 8.275us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.840s 13.449us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.950s 34.387us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.150s 309.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.150s 309.146us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.090s 35.754us 1 1 100.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
clkmgr_csr_aliasing 0.750s 2.008us 0 1 0.00
clkmgr_same_csr_outstanding 0.940s 7.175us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.090s 35.754us 1 1 100.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
clkmgr_csr_aliasing 0.750s 2.008us 0 1 0.00
clkmgr_same_csr_outstanding 0.940s 7.175us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.300s 316.381us 1 1 100.00
clkmgr_tl_intg_err 0.870s 2.317us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.630s 143.896us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.630s 143.896us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.630s 143.896us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.630s 143.896us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.960s 2.146us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.870s 2.317us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.810s 8.275us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.700s 2.511us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.630s 143.896us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.310s 152.247us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.300s 316.381us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.870s 5.938us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.300s 316.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.870s 3.049us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.550s 85.695us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 108521189834485511566650777973664240787816747786369436566692399289009157175832 83
UVM_INFO @ 2511102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 56229367170810705059073524560756597112397032246324333149000929223855492377968 133
UVM_INFO @ 85695383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 101366970182610309187303736300247313196301864777237712638056917318158747407267 84
UVM_INFO @ 13448878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 113567008717485311205746277776064036504279892268174943178719044404946698722546 81
UVM_INFO @ 2146163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 63861655306976731073220633862474215305164379617811395685258729019572797923656 82
UVM_INFO @ 5937967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 114387032533126234517366077205195658545369103366162455835677588388096132707240 82
UVM_INFO @ 8274871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 48031015415584558524654762122167941667692048939160748642061632201220829021768 80
UVM_INFO @ 3048983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_tl_intg_err 914869301261198233513457249056142630447777018124567075215508781650053592692 81
UVM_INFO @ 2317177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 62264587162761130407953485659093654921334350089387194629337139101235103773804 81
UVM_INFO @ 1912286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.io_meas_ctrl_shadowed reset value: * 1 test run
clkmgr_csr_aliasing 51496546223281608597483115710426626013601571160618640471560266395960185332089 83
UVM_INFO @ 2008056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 28321476716794990201042960705807040740014707108145420746421296803133016204149 81
UVM_INFO @ 7174559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---