Simulation Results: csrng

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.05 %
  • code
  • 92.19 %
  • assert
  • 94.54 %
  • func
  • 83.41 %
  • block
  • 96.80 %
  • line
  • 97.63 %
  • branch
  • 92.05 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 18.257us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 19.922us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 31.713us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 20.000s 574.378us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 27.505us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 24.814us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 31.713us 1 1 100.00
csrng_csr_aliasing 2.000s 27.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 119.356us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 154.000s 7276.612us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 154.000s 7276.612us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 61.000s 1777.846us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 42.033us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 26.705us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 7.000s 117.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 7.000s 117.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.922us 1 1 100.00
csrng_csr_rw 2.000s 31.713us 1 1 100.00
csrng_csr_aliasing 2.000s 27.505us 1 1 100.00
csrng_same_csr_outstanding 4.000s 140.469us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.922us 1 1 100.00
csrng_csr_rw 2.000s 31.713us 1 1 100.00
csrng_csr_aliasing 2.000s 27.505us 1 1 100.00
csrng_same_csr_outstanding 4.000s 140.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
csrng_tl_intg_err 11.000s 530.933us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 15.966us 1 1 100.00
csrng_csr_rw 2.000s 31.713us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 119.356us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 61.000s 1777.846us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 119.356us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 61.000s 1777.846us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 119.356us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 11.000s 530.933us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
csrng_sec_cm 6.000s 442.946us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 52.696us 1 1 100.00
csrng_err 3.000s 28.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 4.000s 30.304us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 89531394266141361344435139128576450923060636507862075706513831486377434051040 114
UVM_INFO @ 30303960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---