Simulation Results: dma

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.23 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 65.31 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 1220.460us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 1157.663us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 366.655us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 57.221us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 22.360us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 232.257us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 346.522us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 83.355us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 22.360us 1 1 100.00
dma_csr_aliasing 3.000s 346.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 104.000s 4449.141us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 771.000s 160512.014us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1261.000s 340413.684us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1261.000s 340413.684us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 771.000s 160512.014us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 390.000s 31000.693us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1261.000s 340413.684us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 12.000s 747.368us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 373.000s 108755.790us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 55.071us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 23.939us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 53.606us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 53.606us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 57.221us 1 1 100.00
dma_csr_rw 2.000s 22.360us 1 1 100.00
dma_csr_aliasing 3.000s 346.522us 1 1 100.00
dma_same_csr_outstanding 3.000s 115.461us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 57.221us 1 1 100.00
dma_csr_rw 2.000s 22.360us 1 1 100.00
dma_csr_aliasing 3.000s 346.522us 1 1 100.00
dma_same_csr_outstanding 3.000s 115.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 17.000s 249.061us 1 1 100.00
dma_generic_stress 390.000s 31000.693us 1 1 100.00
dma_handshake_stress 1261.000s 340413.684us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 336.282us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 5.000s 1285.435us 1 1 100.00
dma_sec_cm 1.000s 18.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 103.000s 8589.970us 1 1 100.00
dma_longer_transfer 4.000s 229.581us 1 1 100.00
dma_stress_all_with_rand_reset 21.000s 3653.007us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 24718585474878953307277726071359818139510250913762831417983031148627637464553 112
UVM_INFO @ 3653006635ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---