Simulation Results: edn/edn0

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 79.45 %
  • code
  • 92.09 %
  • assert
  • 98.01 %
  • func
  • 48.25 %
  • block
  • 95.99 %
  • line
  • 98.10 %
  • branch
  • 91.20 %
  • toggle
  • 85.25 %
  • FSM
  • 93.80 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 27.149us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 51.136us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 32.591us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 163.110us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 33.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 23.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 32.591us 1 1 100.00
edn_csr_aliasing 2.000s 33.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 246.547us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 246.547us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 246.547us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 121.614us 1 1 100.00
alerts 1 1 100.00
edn_alert 3.000s 32.681us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 18.842us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 31.939us 1 1 100.00
edn_disable_auto_req_mode 2.000s 56.862us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 13.000s 1050.031us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 52.834us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 86.013us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 5.000s 101.831us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 5.000s 101.831us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 51.136us 1 1 100.00
edn_csr_rw 2.000s 32.591us 1 1 100.00
edn_csr_aliasing 2.000s 33.347us 1 1 100.00
edn_same_csr_outstanding 2.000s 25.207us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 51.136us 1 1 100.00
edn_csr_rw 2.000s 32.591us 1 1 100.00
edn_csr_aliasing 2.000s 33.347us 1 1 100.00
edn_same_csr_outstanding 2.000s 25.207us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 8.000s 2037.617us 1 1 100.00
edn_tl_intg_err 3.000s 96.982us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 19.734us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 3.000s 32.681us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 2037.617us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 2037.617us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 2037.617us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 2037.617us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 3.000s 32.681us 1 1 100.00
edn_sec_cm 8.000s 2037.617us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 3.000s 32.681us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 96.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 55.000s 9021.282us 1 1 100.00