Simulation Results: edn/edn1

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.66 %
  • code
  • 82.79 %
  • assert
  • 97.14 %
  • func
  • 80.04 %
  • line
  • 98.10 %
  • branch
  • 93.51 %
  • cond
  • 87.69 %
  • toggle
  • 86.91 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.170s 20.606us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.190s 16.048us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.980s 97.634us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.290s 147.546us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 24.419us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.610s 39.104us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.980s 97.634us 1 1 100.00
edn_csr_aliasing 1.210s 24.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.390s 82.307us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.390s 82.307us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.390s 82.307us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.120s 55.834us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.600s 36.464us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 40.360us 1 1 100.00
disable 2 2 100.00
edn_disable 1.110s 45.295us 1 1 100.00
edn_disable_auto_req_mode 1.730s 48.941us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.240s 359.193us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.960s 23.523us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.320s 21.961us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.400s 693.879us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.400s 693.879us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.190s 16.048us 1 1 100.00
edn_csr_rw 0.980s 97.634us 1 1 100.00
edn_csr_aliasing 1.210s 24.419us 1 1 100.00
edn_same_csr_outstanding 1.570s 76.315us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.190s 16.048us 1 1 100.00
edn_csr_rw 0.980s 97.634us 1 1 100.00
edn_csr_aliasing 1.210s 24.419us 1 1 100.00
edn_same_csr_outstanding 1.570s 76.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.410s 1065.831us 1 1 100.00
edn_tl_intg_err 2.100s 183.796us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.220s 93.359us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.600s 36.464us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.410s 1065.831us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.410s 1065.831us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.410s 1065.831us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.410s 1065.831us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.600s 36.464us 1 1 100.00
edn_sec_cm 4.410s 1065.831us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.600s 36.464us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.100s 183.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 105.440s 13603.021us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 23052569291076253450355615950060259823302149615952174946871351068861130666942 256
UVM_INFO @ 13603021375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---