Simulation Results: entropy_src/rng_16bits

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.02 %
  • code
  • 80.12 %
  • assert
  • 74.06 %
  • func
  • 49.89 %
  • block
  • 93.65 %
  • line
  • 97.54 %
  • branch
  • 85.00 %
  • toggle
  • 52.50 %
  • FSM
  • 85.42 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 18.699us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 28.703us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 73.318us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 14.000s 4174.081us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.259us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 117.927us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 73.318us 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 3.000s 18.699us 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
entropy_src_fw_ov 135.000s 3706.001us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 135.000s 3706.001us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 190.000s 14148.207us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
entropy_src_intr 18.000s 511.420us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
entropy_src_functional_alerts 8.000s 179.550us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 467.000s 14105.409us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 110.034us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 26.167us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 195.045us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 20.097us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 7.000s 139.233us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 7.000s 139.233us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 28.703us 1 1 100.00
entropy_src_csr_rw 2.000s 73.318us 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.259us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 211.995us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 28.703us 1 1 100.00
entropy_src_csr_rw 2.000s 73.318us 1 1 100.00
entropy_src_csr_aliasing 2.000s 58.259us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 211.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 196.843us 1 1 100.00
entropy_src_tl_intg_err 3.000s 208.314us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
entropy_src_cfg_regwen 2.000s 37.689us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
entropy_src_fw_ov 135.000s 3706.001us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 110.034us 1 1 100.00
entropy_src_sec_cm 3.000s 196.843us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 110.034us 1 1 100.00
entropy_src_sec_cm 3.000s 196.843us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 131.000s 13182.284us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 110.034us 1 1 100.00
entropy_src_sec_cm 3.000s 196.843us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 110.034us 1 1 100.00
entropy_src_sec_cm 3.000s 196.843us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 110.034us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 179.550us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 208.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 471.000s 14024.495us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 2.000s 13.326us 0 1 0.00

Error Messages

   Test seed line log context
UVM_WARNING (uvm_reg_field.svh:1186) [RegModel] Trying to predict value of field 'observe_fifo_depth' while register 'entropy_src_reg_block.observe_fifo_depth' is being accessed 1 test run
entropy_src_stress_all_with_rand_reset 47245410708407235670576235131515111214092103943593900029500843732768259668472 125
UVM_FATAL @ 13325778 ps: (entropy_src_scoreboard.sv:1599) [uvm_test_top.env.scoreboard] Check failed (ral.observe_fifo_depth.observe_fifo_depth.predict( ral.observe_fifo_depth.observe_fifo_depth.get_mirrored_value()-1, .kind(UVM_PREDICT_DIRECT)))
UVM_INFO @ 13325778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_alert. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
entropy_src_fw_ov 99422523842865028409724516357107704330180486179914017421801978792763297107847 479
UVM_INFO @ 3706001239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---