Simulation Results: hmac

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.85 %
  • code
  • 83.02 %
  • assert
  • 97.17 %
  • func
  • 29.35 %
  • block
  • 97.23 %
  • line
  • 98.31 %
  • branch
  • 93.05 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 16.000s 5369.477us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 62.746us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 123.203us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 16.000s 459.574us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 81.131us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 3.000s 43.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 123.203us 1 1 100.00
hmac_csr_aliasing 2.000s 81.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 51.000s 14127.125us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 4.000s 285.761us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 13.000s 886.738us 1 1 100.00
hmac_test_sha384_vectors 33.000s 714.869us 1 1 100.00
hmac_test_sha512_vectors 33.000s 680.738us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 856.526us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 749.240us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 1280.033us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 33.000s 1067.355us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 324.000s 7585.952us 1 1 100.00
error 1 1 100.00
hmac_error 110.000s 28286.151us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 91.000s 4699.656us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 16.000s 5369.477us 1 1 100.00
hmac_long_msg 51.000s 14127.125us 1 1 100.00
hmac_back_pressure 4.000s 285.761us 1 1 100.00
hmac_datapath_stress 324.000s 7585.952us 1 1 100.00
hmac_burst_wr 33.000s 1067.355us 1 1 100.00
hmac_stress_all 211.000s 15267.223us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 16.000s 5369.477us 1 1 100.00
hmac_long_msg 51.000s 14127.125us 1 1 100.00
hmac_back_pressure 4.000s 285.761us 1 1 100.00
hmac_datapath_stress 324.000s 7585.952us 1 1 100.00
hmac_wipe_secret 91.000s 4699.656us 1 1 100.00
hmac_test_sha256_vectors 13.000s 886.738us 1 1 100.00
hmac_test_sha384_vectors 33.000s 714.869us 1 1 100.00
hmac_test_sha512_vectors 33.000s 680.738us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 856.526us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 749.240us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 1280.033us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 16.000s 5369.477us 1 1 100.00
hmac_long_msg 51.000s 14127.125us 1 1 100.00
hmac_back_pressure 4.000s 285.761us 1 1 100.00
hmac_datapath_stress 324.000s 7585.952us 1 1 100.00
hmac_burst_wr 33.000s 1067.355us 1 1 100.00
hmac_error 110.000s 28286.151us 1 1 100.00
hmac_wipe_secret 91.000s 4699.656us 1 1 100.00
hmac_test_sha256_vectors 13.000s 886.738us 1 1 100.00
hmac_test_sha384_vectors 33.000s 714.869us 1 1 100.00
hmac_test_sha512_vectors 33.000s 680.738us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 856.526us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 749.240us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 1280.033us 1 1 100.00
hmac_stress_all 211.000s 15267.223us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 211.000s 15267.223us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 47.990us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 27.932us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 79.100us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 79.100us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 62.746us 1 1 100.00
hmac_csr_rw 2.000s 123.203us 1 1 100.00
hmac_csr_aliasing 2.000s 81.131us 1 1 100.00
hmac_same_csr_outstanding 3.000s 33.657us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 62.746us 1 1 100.00
hmac_csr_rw 2.000s 123.203us 1 1 100.00
hmac_csr_aliasing 2.000s 81.131us 1 1 100.00
hmac_same_csr_outstanding 3.000s 33.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 79.097us 1 1 100.00
hmac_tl_intg_err 5.000s 266.504us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 5.000s 266.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 16.000s 5369.477us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.000s 344.442us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 97.000s 4990.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 19.056us 1 1 100.00