Simulation Results

Simulation Results: keymgr_dpe/darjeeling

10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
65.56 %

code
82.43 %

assert
97.20 %

func
17.04 %

block
97.96 %

line
98.66 %

branch
93.36 %

toggle
56.15 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	16.000s	854.271us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	2.000s	22.589us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	77.531us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	9.000s	1756.903us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	65.121us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	2.000s	102.009us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	77.531us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	65.121us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	1.000s	42.012us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	1.000s	22.180us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	116.574us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	116.574us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	22.589us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	77.531us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	65.121us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.000s	36.264us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	22.589us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	77.531us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	65.121us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.000s	36.264us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	10.000s	1772.535us	1	1	100.00
	keymgr_dpe_tl_intg_err	6.000s	245.746us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.491us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.491us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.491us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	113.491us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.000s	390.239us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	10.000s	1772.535us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	10.000s	1772.535us	1	1	100.00