Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.64 %
  • code
  • 88.92 %
  • assert
  • 96.25 %
  • func
  • 77.74 %
  • block
  • 95.85 %
  • line
  • 96.63 %
  • branch
  • 89.43 %
  • toggle
  • 79.16 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 343.181us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 31.992us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 52.947us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 35.779us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 42.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 22.199us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 52.947us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 42.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 195.034us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.805us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 358.631us 1 1 100.00
lc_ctrl_jtag_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 2143.976us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 7.000s 1698.328us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 1537.758us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 92.503us 1 1 100.00
lc_ctrl_jtag_csr_rw 4.000s 859.529us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 755.823us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 363.519us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 170.513us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 103.759us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 34.637us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 1461.167us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 13.587us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.197s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 30.948us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 137.779us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 137.779us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 31.992us 1 1 100.00
lc_ctrl_csr_rw 1.000s 52.947us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 42.137us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 36.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 31.992us 1 1 100.00
lc_ctrl_csr_rw 1.000s 52.947us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 42.137us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 36.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 123.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 123.002us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 195.034us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 131.313us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 358.631us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 450.283us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 434.581us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 434.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 58941226294184078646297076871159220825674664679070678132557149343159660660362 None
lc_ctrl_state_post_trans 14293642004846624916381447601441536724490666092989253846457837235822514531216 None
lc_ctrl_prog_failure 45734987650821846312680627043525361883858637985251871871127214443904481406819 None
lc_ctrl_errors 64101174697086879197887417827782224152902426766520560461517889948189939777174 None
lc_ctrl_jtag_state_failure 63349710500275509600067728190275016876210366631739798249024205455518168376357 None
lc_ctrl_jtag_state_post_trans 99510098902944714255430230472633175478666103265962345959955229998091317739669 None
lc_ctrl_jtag_prog_failure 56447461038246386836307708277695200923206007643451383913676941659641021654927 None
lc_ctrl_jtag_errors 76604229147447884644568435002298210170410359538229031307323690377149482760839 None
lc_ctrl_sec_mubi 109944958910954580318783865989174272099061423030400872147108681449840335588558 None
lc_ctrl_stress_all 2655511108097867945149189592365426180722137194722978429788991305885882644739 None
lc_ctrl_stress_all_with_rand_reset 70463235544896733748292042089329746524619975777982005027403398592291923201744 None