Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.70 %
  • code
  • 90.54 %
  • assert
  • 96.54 %
  • func
  • 79.03 %
  • block
  • 96.44 %
  • line
  • 97.24 %
  • branch
  • 90.96 %
  • toggle
  • 83.49 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
73.33%
V2S
70.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 243.140us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 27.682us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 34.363us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 37.784us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 53.531us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 19.566us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 34.363us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 53.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 513.705us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 39.933us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 490.498us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 6.000s 2081.573us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 810.507us 1 1 100.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 4.000s 403.358us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 3251.867us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 336.559us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 502.625us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 16.000s 3726.802us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 321.395us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 118.912us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 468.636us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 140.034us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.000s 727.189us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 45.258us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.162s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 20.441us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 24.221us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 24.221us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 27.682us 1 1 100.00
lc_ctrl_csr_rw 2.000s 34.363us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 53.531us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 38.911us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 27.682us 1 1 100.00
lc_ctrl_csr_rw 2.000s 34.363us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 53.531us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 38.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 277.465us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 277.465us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 513.705us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 448.779us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 490.498us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 5.000s 810.507us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 277.482us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 418.913us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 418.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 49336970204929213691628029170093488912743697994369534039696574474527320572956 None
lc_ctrl_state_post_trans 31626691537474381882226533646663996967142490567687715963475867547989622946202 None
lc_ctrl_prog_failure 53903893669562729884197295087238782369769149951419942599741820412544051550535 None
lc_ctrl_errors 26799861333789346379678651852523403634604317108742613781986872434327242732378 None
lc_ctrl_jtag_state_failure 113243156329029207794142868919746607879159112966797243330066140891367037141758 None
lc_ctrl_jtag_prog_failure 86697157985702978891010791159672309871640221326383190824017955735650340983978 None
lc_ctrl_jtag_errors 7041488643639919857604037837347041209631175430898163246677979658845280891445 None
lc_ctrl_sec_mubi 1764637231404314033225605156232524700222060035576233160463945076129561287675 None
lc_ctrl_stress_all 59770405907381428331813471703341842718854907366463008120958532181605260735795 None
lc_ctrl_stress_all_with_rand_reset 110281601067130579682462094946853185081645099169715815697899946077711549160129 None