| V1 |
|
100.00% |
| V2 |
|
81.82% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 36.000s | 8164.879us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 15.035us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 71.953us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 4.000s | 1194.609us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 2.000s | 49.733us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 34.950us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 71.953us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 49.733us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 3.000s | 155.590us | 0 | 1 | 0.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 50.000s | 2190.064us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 18.000s | 9476.194us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 18.000s | 561.498us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 1.000s | 27.805us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 14.877us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 9.834us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 9.834us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 15.035us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 71.953us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 49.733us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 38.059us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 15.035us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 71.953us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 49.733us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 38.059us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 2.000s | 167.287us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 34.748us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched | 1 test run | |||
| mbx_stress | 25881854955684143860634953227681264293656638812382968250766641542111764322450 | 140 |
UVM_INFO @ 155589730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:718) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | 1 test run | |||
| mbx_tl_errors | 17686849544467244297000259652055739183583349251726125043026528720453660517714 | 85 |
TL item was: req: (cip_tl_seq_item@18614) { a_addr: 'h146f2d94 a_data: 'ha419438 a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'h65 a_opcode: 'h1 a_user: 'h24613 d_param: 'h0 d_source: 'h65 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 9834394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|