Simulation Results: otbn

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.09 %
  • code
  • 86.16 %
  • assert
  • 89.66 %
  • func
  • 97.46 %
  • block
  • 99.23 %
  • line
  • 99.43 %
  • branch
  • 94.37 %
  • toggle
  • 84.63 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
76.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 16.000s 47.979us 1 1 100.00
otbn_smoke_vectorized 10.000s 19.392us 1 1 100.00
single_binary 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 7.000s 50.417us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 14.634us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 52.063us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 25.681us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 37.610us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 14.634us 1 1 100.00
otbn_csr_aliasing 6.000s 25.681us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 184.000s 22265.676us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 36.000s 653.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 65.000s 1628.906us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 70.000s 486.487us 0 1 0.00
wfi 0 3 0.00
otbn_wfi_smoke 7.000s 5.484us 0 1 0.00
otbn_wfi_sec_wipe 6.000s 9.224us 0 1 0.00
otbn_wfi_back_to_back 7.000s 6.640us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 96.000s 810.116us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 121.000s 992.949us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 16.000s 55.905us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.378us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 14.000s 159.800us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 17.012us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 15.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 10.000s 477.916us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 10.000s 477.916us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 7.000s 50.417us 1 1 100.00
otbn_csr_rw 5.000s 14.634us 1 1 100.00
otbn_csr_aliasing 6.000s 25.681us 1 1 100.00
otbn_same_csr_outstanding 4.000s 39.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 7.000s 50.417us 1 1 100.00
otbn_csr_rw 5.000s 14.634us 1 1 100.00
otbn_csr_aliasing 6.000s 25.681us 1 1 100.00
otbn_same_csr_outstanding 4.000s 39.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 22.790us 1 1 100.00
otbn_dmem_err 16.000s 88.240us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 15.000s 66.499us 1 1 100.00
otbn_controller_ispr_rdata_err 13.000s 55.780us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 55.970us 1 1 100.00
otbn_urnd_err 7.000s 10.292us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 11.814us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 9.000s 43.162us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 9.000s 25.672us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
otbn_tl_intg_err 28.000s 631.373us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 66.000s 182.774us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 16.000s 47.979us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 16.000s 88.240us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 22.790us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 28.000s 631.373us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 55.905us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 22.790us 1 1 100.00
otbn_dmem_err 16.000s 88.240us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.378us 1 1 100.00
otbn_illegal_mem_acc 9.000s 11.814us 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 22.790us 1 1 100.00
otbn_dmem_err 16.000s 88.240us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.378us 1 1 100.00
otbn_illegal_mem_acc 9.000s 11.814us 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 55.905us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 22.790us 1 1 100.00
otbn_dmem_err 16.000s 88.240us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.378us 1 1 100.00
otbn_illegal_mem_acc 9.000s 11.814us 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 40.089us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 39.976us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 87.000s 204.518us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 87.000s 204.518us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 13.000s 29.929us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 13.000s 113.360us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 46.804us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 46.804us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 35.153us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 96.000s 810.116us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 29.395us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 22.000s 152.401us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 522.000s 3432.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 9.000s 78.177us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 88484798757338126991553861681643921670078252767004571469347186782640407297643 111
UVM_INFO @ 5484388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 41222880841306809716442499122820263776216844380607081374398326548519754023567 113
UVM_INFO @ 6639576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 44487745538996501421088357175781027006506475105541022714406228634268517730176 373
UVM_INFO @ 486487433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 1 test run
otbn_stress_all_with_rand_reset 18843978353234707056384400658687458334150898021600925736553917001927557974050 148
UVM_INFO @ 78177328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. 1 test run
otbn_wfi_sec_wipe 111477548205215551469090843387644466515335074255912197789923470205356605686082 111
UVM_FATAL @ 9223975 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 9223975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---