Simulation Results: otp_ctrl

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.79 %
  • code
  • 72.21 %
  • assert
  • 93.47 %
  • func
  • 55.68 %
  • line
  • 87.48 %
  • branch
  • 84.14 %
  • cond
  • 86.04 %
  • toggle
  • 66.63 %
  • FSM
  • 36.74 %
Validation stages
V1
100.00%
V2
70.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.170s 100.964us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.510s 92.630us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.490s 47.677us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.450s 703.102us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.730s 335.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.210s 252.393us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.490s 47.677us 1 1 100.00
otp_ctrl_csr_aliasing 3.730s 335.918us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.260s 44.309us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.160s 56.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 143.580s 2786.272us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.270s 2318.708us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 4.320s 1647.780us 0 1 0.00
otp_ctrl_check_fail 11.590s 2031.214us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.380s 603.799us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.170s 4856.946us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 25.870s 2598.923us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 14.910s 1888.649us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 23.050s 3002.736us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 20.200s 1322.830us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 9.520s 998.362us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.410s 89.889us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.400s 69.336us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 9.750s 625.104us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 9.750s 625.104us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.510s 92.630us 1 1 100.00
otp_ctrl_csr_rw 2.490s 47.677us 1 1 100.00
otp_ctrl_csr_aliasing 3.730s 335.918us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.210s 59.746us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.510s 92.630us 1 1 100.00
otp_ctrl_csr_rw 2.490s 47.677us 1 1 100.00
otp_ctrl_csr_aliasing 3.730s 335.918us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.210s 59.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
otp_ctrl_tl_intg_err 34.410s 5719.632us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 34.410s 5719.632us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_ctrl_macro_errs 23.050s 3002.736us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_ctrl_macro_errs 23.050s 3002.736us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.970s 364.959us 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.270s 2318.708us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 11.590s 2031.214us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 7.000s 575.814us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 452.440s 37339.883us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.380s 603.799us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.810s 526.708us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 23.050s 3002.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 168.290s 62559.787us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 13.640s 1786.735us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_background_chks 25071914280891535362541848429468774794311113640428246998695576409287777757429 1308
UVM_INFO @ 1647780485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 102902955256552568865304738391672423966591115714455610199587641752759588165624 6539
UVM_INFO @ 998361701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 9235422344251695125457610208375486624367460341799231921337405508006927514232 4165
UVM_INFO @ 575814468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8888230384870102328763813739463137614078130454261109157335245033622894854148 3791
UVM_INFO @ 1786735399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_partition_walk 83100280491478456870689016929075053150723760822797761205298744625955351692354 160061
UVM_INFO @ 2786272110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 91103615841987970384359461251421814946308190327206056573492354107570007185269 95
UVM_INFO @ 62559787233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error 1 test run
otp_ctrl_dai_errs 55252645274167262268965950820998439358316884136471591670108961078515973095543 6854
UVM_INFO @ 1888649320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_check_error has unexpected timeout error 1 test run
otp_ctrl_check_fail 89283579608889512053825248548915837043451346557876172426242443412317362530017 5680
UVM_INFO @ 2031213791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---