Simulation Results: rom_ctrl/32kb

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.64 %
  • code
  • 79.56 %
  • assert
  • 96.65 %
  • func
  • 86.70 %
  • block
  • 78.32 %
  • line
  • 78.74 %
  • branch
  • 78.84 %
  • toggle
  • 84.48 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 768.081us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 92.915us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 57.846us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 61.889us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.329us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 77.461us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 57.846us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.329us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 82.953us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 49.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 8.532us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 65.512us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 122.818us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 405.442us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 405.442us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 92.915us 1 1 100.00
rom_ctrl_csr_rw 3.000s 57.846us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.329us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 62.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 92.915us 1 1 100.00
rom_ctrl_csr_rw 3.000s 57.846us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.329us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 62.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 1416.687us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 62.000s 1451.067us 1 1 100.00
rom_ctrl_tl_intg_err 30.000s 350.230us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 62.000s 1451.067us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 62.000s 1451.067us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 62.000s 1451.067us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 62.000s 1451.067us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 768.081us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 768.081us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 768.081us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 30.000s 350.230us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 65.512us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 1416.687us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 62.000s 1451.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_stress_all 46271360672978416415197988579505878568718260245350519453095850166203604253178 None
rom_ctrl_corrupt_sig_fatal_chk 54825940801667589177014912597465945620566756404020756979461609860776307728736 None
rom_ctrl_stress_all_with_rand_reset 101876118448810055696867206189146764663701804341600016303139250977196297250081 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 27011778963612631811879231344959423669946599677178615312149891622290566815901 88
UVM_INFO @ 8532106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---