Simulation Results: rom_ctrl/64kb

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 80.70 %
  • code
  • 79.50 %
  • assert
  • 97.53 %
  • func
  • 65.08 %
  • block
  • 78.32 %
  • line
  • 78.74 %
  • branch
  • 78.84 %
  • toggle
  • 84.22 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 399.293us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 74.116us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 67.800us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 128.187us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 71.565us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 56.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 67.800us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 71.565us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 50.279us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 60.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 4.322us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 10.000s 870.302us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 61.304us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 156.477us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 156.477us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 74.116us 1 1 100.00
rom_ctrl_csr_rw 4.000s 67.800us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 71.565us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 70.823us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 74.116us 1 1 100.00
rom_ctrl_csr_rw 4.000s 67.800us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 71.565us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 70.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 414.232us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 254.000s 929.002us 1 1 100.00
rom_ctrl_tl_intg_err 30.000s 204.621us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 254.000s 929.002us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 254.000s 929.002us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 254.000s 929.002us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 254.000s 929.002us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 399.293us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 399.293us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 399.293us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 30.000s 204.621us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 10.000s 870.302us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 414.232us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 254.000s 929.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_stress_all 20038845009033801236595490944576644502024655045234357706753057259835993015790 None
rom_ctrl_corrupt_sig_fatal_chk 93154620384399889197188947439504324750545686708521400481434805171298961810242 None
rom_ctrl_stress_all_with_rand_reset 75888975210925500942106755064538725026316262639005341852102699447375139672957 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 100099109085908300561941233017330042223937404695029029657516644190915220241995 88
UVM_INFO @ 4322325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---