Simulation Results: rstmgr

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.19 %
  • code
  • 99.41 %
  • assert
  • 98.17 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.09 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.690s 63.486us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.620s 91.910us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.110s 35.495us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.030s 136.173us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.320s 37.750us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.160s 94.534us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.110s 35.495us 1 1 100.00
rstmgr_csr_aliasing 1.320s 37.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.050s 143.153us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.520s 46.098us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.490s 65.724us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.130s 606.125us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.130s 606.125us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.130s 606.125us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.130s 606.125us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 42.730s 5994.162us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.170s 37.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.820s 47.509us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.820s 47.509us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.620s 91.910us 1 1 100.00
rstmgr_csr_rw 1.110s 35.495us 1 1 100.00
rstmgr_csr_aliasing 1.320s 37.750us 1 1 100.00
rstmgr_same_csr_outstanding 1.730s 47.702us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.620s 91.910us 1 1 100.00
rstmgr_csr_rw 1.110s 35.495us 1 1 100.00
rstmgr_csr_aliasing 1.320s 37.750us 1 1 100.00
rstmgr_same_csr_outstanding 1.730s 47.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 44.160s 6800.852us 1 1 100.00
rstmgr_tl_intg_err 5.050s 699.526us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 44.160s 6800.852us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 44.160s 6800.852us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 5.050s 699.526us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.700s 67.951us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.920s 472.341us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.190s 292.173us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 44.160s 6800.852us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.110s 35.495us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.110s 35.495us 1 1 100.00