Simulation Results: rv_dm/use_dmi_interface

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.57 %
  • code
  • 73.78 %
  • assert
  • 96.90 %
  • func
  • 92.02 %
  • block
  • 89.63 %
  • line
  • 89.42 %
  • branch
  • 71.87 %
  • toggle
  • 71.35 %
  • FSM
  • 62.50 %
Validation stages
V1
92.59%
V2
69.57%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 48.000s 2564.838us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 53.000s 183.633us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 43.000s 127.846us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 51.000s 2939.780us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 45.000s 652.782us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 52.000s 2414.904us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 66.000s 8748.599us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 65.000s 62423.724us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 43.000s 6668.620us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 49.000s 509.328us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 47.000s 283.746us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 41.000s 352.471us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 44.000s 342.704us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 51.000s 517.414us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 48.000s 841.937us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 46.000s 274.100us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 54.000s 911.315us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 49.000s 509.328us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 47.000s 433.611us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 51.000s 223.079us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 41.000s 352.471us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 51.000s 22.411us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 45.000s 141.252us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 49.000s 182.893us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 78.000s 28176.255us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 54.000s 4610.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 51.000s 83.682us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 54.000s 4610.775us 1 1 100.00
rv_dm_csr_rw 49.000s 182.893us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 45.000s 34.268us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 39.000s 101.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 48.000s 2564.838us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 52.000s 592.106us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 39.000s 337.655us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 51.000s 720.476us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 46.000s 756.648us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 52.000s 2607.754us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 52.000s 141.446us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 41.000s 1589.469us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 38.000s 72.442us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 38.000s 108.891us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 39.000s 1019.585us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 44.000s 204.238us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 50.000s 68.479us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 74.000s 7990.448us 1 1 100.00
rv_dm_tap_fsm_rand_reset 115.000s 5096.078us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 44.000s 94.254us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 42.000s 489.591us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 44.000s 82.441us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 41.000s 176.367us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 41.000s 176.367us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 54.000s 4610.775us 1 1 100.00
rv_dm_csr_hw_reset 45.000s 141.252us 1 1 100.00
rv_dm_csr_rw 49.000s 182.893us 1 1 100.00
rv_dm_same_csr_outstanding 38.000s 192.225us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 54.000s 4610.775us 1 1 100.00
rv_dm_csr_hw_reset 45.000s 141.252us 1 1 100.00
rv_dm_csr_rw 49.000s 182.893us 1 1 100.00
rv_dm_same_csr_outstanding 38.000s 192.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 40.000s 1475.192us 1 1 100.00
rv_dm_tl_intg_err 46.000s 1403.045us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 46.000s 1403.045us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 39.000s 1019.585us 1 1 100.00
rv_dm_debug_disabled 49.000s 43.017us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 39.000s 1019.585us 1 1 100.00
rv_dm_debug_disabled 49.000s 43.017us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 48.000s 2564.838us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 52.000s 313.689us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 39.000s 267.339us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 39.000s 267.339us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 52.000s 313.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 56.000s 585.836us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 200.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 25348632332471226848373136559381180798978287676085364113872016601793358562034 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23836
rv_dm_bad_sba_tl_access 95924238406117499513919198174704137907959058070464278711199834295309793513515 96
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23782
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 2 test runs
rv_dm_delayed_resp_sba_tl_access 103531288825656588146839001971527732664989329318778440997619075142591373294212 107
UVM_INFO @ 141445884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 23738897128751744999517786089274251344394740121782491819294997870720306886745 107
UVM_INFO @ 72441567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 64752634629575007274532203871255217265244361522575442400605989657299497855655 87
UVM_INFO @ 68479191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 43627158404006689924469799380603066496870486373251503871118130253618679561833 88
UVM_INFO @ 489591301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 39705110287352694190878228056097712700155369371719531796395594953534735768009 87
UVM_INFO @ 342703933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 4203084328438551002317278548442852985748138707241241425234623552268651269972 87
UVM_INFO @ 108891464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@23888) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 30015136199379024139217140282099583229797366148083228300227590659611120334611 87
).
UVM_INFO @ 22410547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 42226494888291313556015380973413208602844965541912927943851748435718380388359 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done) 1 test run
rv_dm_stress_all_with_rand_reset 99877570520104999160585138540980218490041244762569839647341779768911153881514 109
UVM_INFO @ 585836034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---