Simulation Results: rv_timer

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 96.08 %
  • code
  • 90.45 %
  • assert
  • 97.78 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 45.841us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 16.904us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 2.000s 30.461us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 154.749us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 20.115us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 39.710us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 2.000s 30.461us 1 1 100.00
rv_timer_csr_aliasing 2.000s 20.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 374.238us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 4.000s 1078.505us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 323.000s 1349165.143us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 323.000s 1349165.143us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 11.000s 3529.995us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 39.694us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 2.000s 144.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 119.613us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 119.613us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 16.904us 1 1 100.00
rv_timer_csr_rw 2.000s 30.461us 1 1 100.00
rv_timer_csr_aliasing 2.000s 20.115us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 172.273us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 2.000s 16.904us 1 1 100.00
rv_timer_csr_rw 2.000s 30.461us 1 1 100.00
rv_timer_csr_aliasing 2.000s 20.115us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 172.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 247.361us 1 1 100.00
rv_timer_tl_intg_err 2.000s 451.537us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 451.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 390.828us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 3.000s 767.571us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 27.000s 2502.091us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 32395873148275409795735029430037510073845852870744092969098905871511699691001 86
UVM_INFO @ 390828316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 42035640505469927720932303804095002947567850922636913970443469152055768582612 84
UVM_INFO @ 767571041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---