Simulation Results: spi_host

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.99 %
  • code
  • 91.14 %
  • assert
  • 96.60 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 39.000s 2308.734us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 57.943us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 18.548us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 133.721us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 134.291us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 93.645us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 18.548us 1 1 100.00
spi_host_csr_aliasing 2.000s 134.291us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 7.000s 40.379us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 37.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 3.000s 27.555us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 185.459us 1 1 100.00
spi_host_error_cmd 2.000s 23.189us 1 1 100.00
spi_host_event 7.000s 488.745us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 82.887us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 82.887us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 82.887us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 229.000s 22695.727us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 36.000s 3086.147us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 41.666us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 82.887us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 82.887us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 39.000s 2308.734us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 39.000s 2308.734us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 5.000s 243.679us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 2814.168us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 226.000s 110255.587us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 160.982us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 185.459us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 16.125us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 18.907us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 50.432us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 50.432us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 57.943us 1 1 100.00
spi_host_csr_rw 2.000s 18.548us 1 1 100.00
spi_host_csr_aliasing 2.000s 134.291us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 107.078us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 57.943us 1 1 100.00
spi_host_csr_rw 2.000s 18.548us 1 1 100.00
spi_host_csr_aliasing 2.000s 134.291us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 107.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 3.000s 114.284us 1 1 100.00
spi_host_sec_cm 2.000s 109.937us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 3.000s 114.284us 1 1 100.00