Simulation Results: sram_ctrl/main

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.21 %
  • code
  • 93.73 %
  • assert
  • 97.69 %
  • func
  • 94.20 %
  • block
  • 92.73 %
  • line
  • 93.64 %
  • branch
  • 89.45 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 369.191us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 21.135us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 54.258us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 232.804us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.122us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1438.243us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 54.258us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.122us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 260.000s 6031.771us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 156.000s 4847.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 55.000s 25061.931us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 147.000s 10400.986us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 181.000s 15475.997us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 69.000s 43375.373us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 37.000s 30896.173us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 38.000s 7808.233us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 714.444us 1 1 100.00
sram_ctrl_partial_access_b2b 357.000s 114778.109us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 1080.519us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 3698.446us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 1367.660us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 14.000s 6966.786us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1342.298us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 369.191us 1 1 100.00
sram_ctrl_partial_access 6.000s 714.444us 1 1 100.00
sram_ctrl_access_during_key_req 69.000s 43375.373us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 145.000s 26983.336us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 30.278us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 306.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 306.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.135us 1 1 100.00
sram_ctrl_csr_rw 2.000s 54.258us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.122us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.314us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.135us 1 1 100.00
sram_ctrl_csr_rw 2.000s 54.258us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 45.122us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 14151.520us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1516.956us 1 1 100.00
sram_ctrl_tl_intg_err 4.000s 376.748us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1516.956us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 4.000s 376.748us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 6966.786us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 6966.786us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 54.258us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 38.000s 7808.233us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 38.000s 7808.233us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 38.000s 7808.233us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 37.000s 30896.173us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 14151.520us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 369.191us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 369.191us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 38.000s 7808.233us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1516.956us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 37.000s 30896.173us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1516.956us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1516.956us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 369.191us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1516.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 14.000s 399.709us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 80769227196122433309879198187499144668556857236999987892589304572123039980911 None
sram_ctrl_mubi_enc_err 74046060018695335768088166654678158158252244953759085613730996735834149072605 None