Simulation Results: sram_ctrl/ret

 
10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.95 %
  • code
  • 81.50 %
  • assert
  • 97.95 %
  • func
  • 93.40 %
  • block
  • 91.85 %
  • line
  • 93.41 %
  • branch
  • 87.60 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 54.241us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 16.911us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.879us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 105.269us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 23.756us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 104.025us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 18.879us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 23.756us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 11.000s 819.522us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 330.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 192.955us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 178.000s 13026.393us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 568.277us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 15.000s 455.475us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.000s 5077.559us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 300.898us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 153.044us 1 1 100.00
sram_ctrl_partial_access_b2b 261.000s 10699.499us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 38.640us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 50.687us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 40.758us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 727.871us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 89.790us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 54.241us 1 1 100.00
sram_ctrl_partial_access 2.000s 153.044us 1 1 100.00
sram_ctrl_access_during_key_req 15.000s 455.475us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 34.000s 2025.784us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 58.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 294.490us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 294.490us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 16.911us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.879us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 23.756us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 41.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 16.911us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.879us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 23.756us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 41.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 823.154us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1218.710us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 389.555us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1218.710us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 389.555us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 727.871us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 727.871us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.879us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 300.898us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 300.898us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 300.898us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.000s 5077.559us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 823.154us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 54.241us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 54.241us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 300.898us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1218.710us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.000s 5077.559us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1218.710us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1218.710us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 54.241us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1218.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 93.000s 5891.889us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 35019633349156763532373747489299312610304463192763395175921313900719108289421 None
sram_ctrl_mubi_enc_err 22830480242547095719039601372234355735925181233576719092400076901064034033629 None