Simulation Results

Simulation Results: uart

10/09/2026 15:31:28 DVSim: v1.52.2 sha: 1133189 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
93.93 %

code
92.53 %

assert
98.56 %

func
90.69 %

block
98.83 %

line
99.24 %

branch
97.79 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		90.91%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	13.000s	6150.114us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	2.000s	51.649us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	15.347us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	2298.135us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	2.000s	38.781us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	76.225us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	15.347us	1	1	100.00
	uart_csr_aliasing	2.000s	38.781us	1	1	100.00

20/22 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	75.000s	337659.599us	1	1	100.00
parity				2	2	100.00
	uart_smoke	13.000s	6150.114us	1	1	100.00
	uart_tx_rx	75.000s	337659.599us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	27.000s	46166.778us	1	1	100.00
	uart_rx_parity_err	27.000s	19689.631us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	75.000s	337659.599us	1	1	100.00
	uart_intr	27.000s	46166.778us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	37.000s	50127.673us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	22.000s	100737.310us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	25.000s	109967.761us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	27.000s	46166.778us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	27.000s	46166.778us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	27.000s	46166.778us	1	1	100.00
perf				1	1	100.00
	uart_perf	67.000s	4261.031us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	6.000s	1665.182us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	6.000s	1665.182us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	9.000s	9554.276us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	5.000s	24939.669us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	4.000s	837.092us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	7.000s	3658.320us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	473.000s	85006.202us	1	1	100.00
stress_all				0	1	0.00
	uart_stress_all	161.000s	275801.049us	0	1	0.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	35.508us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	2.000s	15.851us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	3.000s	399.303us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	3.000s	399.303us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	2.000s	51.649us	1	1	100.00
	uart_csr_rw	1.000s	15.347us	1	1	100.00
	uart_csr_aliasing	2.000s	38.781us	1	1	100.00
	uart_same_csr_outstanding	2.000s	114.130us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	2.000s	51.649us	1	1	100.00
	uart_csr_rw	1.000s	15.347us	1	1	100.00
	uart_csr_aliasing	2.000s	38.781us	1	1	100.00
	uart_same_csr_outstanding	2.000s	114.130us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	138.357us	1	1	100.00
	uart_tl_intg_err	2.000s	61.260us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	61.260us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	13.000s	1069.520us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				2 test runs
	uart_noise_filter	69375940799555214302312707840433253288586514489011560733254770474287761179690	87	UVM_ERROR @ 8463753998 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 8463917262 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (160 [0xa0] vs 251 [0xfb]) reg name: uart_reg_block.rdata UVM_ERROR @ 8937137966 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 15, clk_pulses: 0 UVM_ERROR @ 8937178782 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_stress_all	996322297691455556164787349496037683612502255172636441765511675414437768130	102	UVM_ERROR @ 273444480054 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 273445003863 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (93 [0x5d] vs 245 [0xf5]) reg name: uart_reg_block.rdata UVM_ERROR @ 273573051354 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0 UVM_ERROR @ 273573146592 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty