Simulation Results: aes/gcm_masked

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.27 %
  • code
  • 95.70 %
  • assert
  • 98.43 %
  • func
  • 64.68 %
  • block
  • 95.84 %
  • line
  • 97.54 %
  • branch
  • 89.80 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 102.629us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 192.708us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 3.000s 105.104us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 93.829us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 254.112us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 104.289us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 63.574us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 93.829us 1 1 100.00
aes_csr_aliasing 2.000s 104.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 192.708us 1 1 100.00
aes_config_error 3.000s 96.150us 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 192.708us 1 1 100.00
aes_config_error 3.000s 96.150us 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
back2back 1 2 50.00
aes_stress 6.000s 91.807us 1 1 100.00
aes_b2b 4.000s 121.178us 0 1 0.00
backpressure 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 4.000s 192.708us 1 1 100.00
aes_config_error 3.000s 96.150us 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
aes_alert_reset 3602.000s 0.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 102.325us 1 1 100.00
aes_config_error 3.000s 96.150us 1 1 100.00
aes_alert_reset 3602.000s 0.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 6.000s 257.897us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 349.044us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 11.000s 777.485us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 3602.000s 0.000us 0 1 0.00
stress 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
sideload 2 2 100.00
aes_stress 6.000s 91.807us 1 1 100.00
aes_sideload 3.000s 107.400us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 112.773us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 54.000s 3498.988us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 91.426us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 76.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 130.084us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 130.084us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 3.000s 105.104us 1 1 100.00
aes_csr_rw 3.000s 93.829us 1 1 100.00
aes_csr_aliasing 2.000s 104.289us 1 1 100.00
aes_same_csr_outstanding 2.000s 86.197us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 3.000s 105.104us 1 1 100.00
aes_csr_rw 3.000s 93.829us 1 1 100.00
aes_csr_aliasing 2.000s 104.289us 1 1 100.00
aes_same_csr_outstanding 2.000s 86.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 15.028us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 810.545us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 9.000s 1817.476us 1 1 100.00
aes_tl_intg_err 3.000s 187.647us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 187.647us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 3602.000s 0.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 4.000s 192.708us 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
aes_alert_reset 3602.000s 0.000us 0 1 0.00
aes_core_fi 31.000s 10011.919us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 4.000s 91.426us 1 1 100.00
aes_config_error 3.000s 96.150us 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
aes_core_fi 31.000s 10011.919us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.575us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 506.259us 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 6.000s 91.807us 1 1 100.00
aes_sideload 3.000s 107.400us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 506.259us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 506.259us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 506.259us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 506.259us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 506.259us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 6.000s 91.807us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3600.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
aes_ctr_fi 2.000s 49.500us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3600.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3600.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_ctr_fi 2.000s 49.500us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
aes_ctr_fi 2.000s 49.500us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 3602.000s 0.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
aes_ctr_fi 2.000s 49.500us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
aes_ctr_fi 2.000s 49.500us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_ctr_fi 2.000s 49.500us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 98.227us 1 1 100.00
aes_fi 3600.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3600.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 90.051us 1 1 100.00
aes_cipher_fi 2.000s 50.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 14.482us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_alert_reset 23454746554378312647186965300244486520702648279595549238379834631971932263192 None
aes_fi 58688853435077167041212366034693712293191381785714688232916019227790073877673 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert recov_ctrl_update_err has unexpected timeout error 1 test run
aes_b2b 93238057761818298971155951619933505762009826960536187365140963624319811219901 9262
UVM_INFO @ 121178166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 61528576265726639806859866135512277234735410714349157170136646461710508547877 3538
UVM_INFO @ 15028405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 46520246660299166071739145659846147207423713381681372142305013898076683062236 146
UVM_INFO @ 10011919129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 65995367878451103681097195313667697773288680634150180893259262298843306313368 165
UVM_INFO @ 14482246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---