Simulation Results: aes/gcm_unmasked

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.07 %
  • code
  • 91.47 %
  • assert
  • 97.94 %
  • func
  • 62.81 %
  • block
  • 91.00 %
  • line
  • 92.97 %
  • branch
  • 84.12 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 97.549us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 113.857us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 85.644us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 65.750us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 199.172us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 93.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 68.384us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 65.750us 1 1 100.00
aes_csr_aliasing 2.000s 93.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 113.857us 1 1 100.00
aes_config_error 3.000s 58.749us 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 113.857us 1 1 100.00
aes_config_error 3.000s 58.749us 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 61.466us 1 1 100.00
aes_b2b 4.000s 71.080us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 113.857us 1 1 100.00
aes_config_error 3.000s 58.749us 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
aes_alert_reset 2.000s 103.478us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 73.621us 1 1 100.00
aes_config_error 3.000s 58.749us 1 1 100.00
aes_alert_reset 2.000s 103.478us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 105.956us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 491.549us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 103.478us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 61.466us 1 1 100.00
aes_sideload 3.000s 256.953us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 5.000s 1552.262us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10801.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 85.184us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 79.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 79.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 85.644us 1 1 100.00
aes_csr_rw 2.000s 65.750us 1 1 100.00
aes_csr_aliasing 2.000s 93.151us 1 1 100.00
aes_same_csr_outstanding 2.000s 99.937us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 85.644us 1 1 100.00
aes_csr_rw 2.000s 65.750us 1 1 100.00
aes_csr_aliasing 2.000s 93.151us 1 1 100.00
aes_same_csr_outstanding 2.000s 99.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 414.037us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 134.178us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 897.416us 1 1 100.00
aes_tl_intg_err 3.000s 192.919us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 192.919us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 103.478us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 113.857us 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
aes_alert_reset 2.000s 103.478us 1 1 100.00
aes_core_fi 2141.000s 200000.000us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 3.000s 58.749us 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
aes_core_fi 2141.000s 200000.000us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 469.203us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 65.049us 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 61.466us 1 1 100.00
aes_sideload 3.000s 256.953us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.049us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.049us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 65.049us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 65.049us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 65.049us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 61.466us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 165.889us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
aes_ctr_fi 2.000s 84.569us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 165.889us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 165.889us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_ctr_fi 2.000s 84.569us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 165.889us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
aes_ctr_fi 2.000s 84.569us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 103.478us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
aes_ctr_fi 2.000s 84.569us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
aes_ctr_fi 2.000s 84.569us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_ctr_fi 2.000s 84.569us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 165.889us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 165.889us 0 1 0.00
aes_control_fi 2.000s 59.244us 1 1 100.00
aes_cipher_fi 3.000s 52.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 30.290us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 18833070821304987692941816257109671516577693219632112381972099424727664081340 5085
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_core_fi 27308081300568075023715397749657919494817873863852849546003858535034772676083 148
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_stress_all 6306424997443068223293524772904125056524573173392510375369068687748303852686 None
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 40286141092350794665159222203362441657543863959629963065406841181931078212083 168
UVM_INFO @ 30289762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---