Simulation Results: alert_handler

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.79 %
  • code
  • 87.78 %
  • assert
  • 97.57 %
  • func
  • 75.02 %
  • line
  • 99.57 %
  • branch
  • 98.09 %
  • cond
  • 91.47 %
  • toggle
  • 85.23 %
  • FSM
  • 64.52 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 10.750s 210.038us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.220s 188.091us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.620s 110.935us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 339.150s 20775.746us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 83.430s 1106.302us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 11.270s 764.037us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.620s 110.935us 1 1 100.00
alert_handler_csr_aliasing 83.430s 1106.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 431.540s 8143.945us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 8.840s 507.638us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 3535.500s 77487.181us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 27.080s 457.026us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 10.750s 210.038us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 34.420s 2617.079us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 32.740s 920.775us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 197.450s 4176.761us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 982.840s 13212.491us 1 1 100.00
alert_handler_lpg_stub_clk 3338.410s 655207.878us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 248.180s 6283.204us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 17.960s 1029.807us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.410s 60.066us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.840s 16.358us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 33.360s 1362.710us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 33.360s 1362.710us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.220s 188.091us 1 1 100.00
alert_handler_csr_rw 5.620s 110.935us 1 1 100.00
alert_handler_csr_aliasing 83.430s 1106.302us 1 1 100.00
alert_handler_same_csr_outstanding 23.140s 204.746us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.220s 188.091us 1 1 100.00
alert_handler_csr_rw 5.620s 110.935us 1 1 100.00
alert_handler_csr_aliasing 83.430s 1106.302us 1 1 100.00
alert_handler_same_csr_outstanding 23.140s 204.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 185.130s 2327.057us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 185.130s 2327.057us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 185.130s 2327.057us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 185.130s 2327.057us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1268.650s 16110.424us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
alert_handler_tl_intg_err 3.230s 52.029us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.230s 52.029us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 185.130s 2327.057us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 10.750s 210.038us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 10.750s 210.038us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 10.750s 210.038us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 10.750s 210.038us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 27.080s 457.026us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 982.840s 13212.491us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 27.080s 457.026us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3535.500s 77487.181us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3535.500s 77487.181us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 32.510s 2070.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 26.750s 1873.519us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 31798338815605784623012461431911613443609871413737990124911131424945090704922 108
UVM_INFO @ 4176760623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 48892578679245935993254882402487097289031473631828287861969310356219249000696 212
UVM_INFO @ 1029807282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 30822214544076878412040713912886522591376873265282300407181158799391322087399 95
UVM_INFO @ 1873519272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---