Simulation Results: clkmgr

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.22 %
  • code
  • 69.09 %
  • assert
  • 88.84 %
  • func
  • 70.73 %
  • line
  • 82.12 %
  • branch
  • 87.53 %
  • cond
  • 77.13 %
  • toggle
  • 98.68 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.280s 17.567us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.890s 16.147us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.840s 82.791us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.800s 5.261us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.780s 4.287us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
clkmgr_csr_aliasing 0.800s 5.261us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.200s 16.427us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.260s 25.542us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.000s 15.901us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.280s 17.567us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.760s 6.637us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.880s 3.839us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.760s 6.637us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.390s 54.585us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.060s 46.908us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.100s 103.433us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.100s 103.433us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.890s 16.147us 1 1 100.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
clkmgr_csr_aliasing 0.800s 5.261us 0 1 0.00
clkmgr_same_csr_outstanding 1.230s 19.680us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.890s 16.147us 1 1 100.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
clkmgr_csr_aliasing 0.800s 5.261us 0 1 0.00
clkmgr_same_csr_outstanding 1.230s 19.680us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 11.840s 953.164us 1 1 100.00
clkmgr_tl_intg_err 0.990s 5.171us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 37.765us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 37.765us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 37.765us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 37.765us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.910s 3.055us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.990s 5.171us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.760s 6.637us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.880s 3.839us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.610s 37.765us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.570s 30.326us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 11.840s 953.164us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.900s 14.064us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 11.840s 953.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 1.060s 10.277us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.670s 66.248us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 27469619003127328049331584505754864029161883559927564315413019985832179715169 82
UVM_INFO @ 6637277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 7317764210325002178888238218311407068463951944683662766413047761493724916405 112
UVM_INFO @ 66248069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 82670453272058453356884897376987923293127350692764121877654370688909240239921 82
UVM_INFO @ 54585447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_tl_intg_err 36862537886189491148680040261645231176088136701326460123168298693327074831420 91
UVM_INFO @ 5171022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 38253709767900972159029306370939518743133762000924729379725638684486189448552 82
UVM_INFO @ 14063839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 49910244316299315114626088918479544000149675626190624462785281965071691817748 82
UVM_INFO @ 4287290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 24568033005173145358471716330357919121178747152914525901594763548623126006337 81
UVM_INFO @ 3054737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 31809929012060708815422454709240677507542503308759247961774125100874513461618 84
UVM_INFO @ 5260835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 47003433757836599203795432748198734364748708747833741140229479074940684408115 84
UVM_INFO @ 3839294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 79772466051558791719500073662133880168315798267696451689540697230412231599203 80
UVM_INFO @ 10277127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 75429943570413567564479513563363839437376282179327403073389834493720827287137 81
UVM_INFO @ 82790957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 92877871143257806530978653677797555076916765951912167704069722948672842808574 81
UVM_INFO @ 19679569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---