Simulation Results: dma

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.59 %
  • code
  • 90.76 %
  • assert
  • 96.50 %
  • func
  • 60.51 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 1100.373us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 9.000s 453.420us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 8.000s 1154.243us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 51.721us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 28.385us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 946.368us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 40.268us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 28.339us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 28.385us 1 1 100.00
dma_csr_aliasing 2.000s 40.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 96.000s 5032.465us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 279.000s 43255.658us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 351.000s 178131.117us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 351.000s 178131.117us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 279.000s 43255.658us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 152.000s 19161.071us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 351.000s 178131.117us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 12.000s 9853.423us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 231.000s 25124.323us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 37.540us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 105.046us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 184.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 184.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 51.721us 1 1 100.00
dma_csr_rw 2.000s 28.385us 1 1 100.00
dma_csr_aliasing 2.000s 40.268us 1 1 100.00
dma_same_csr_outstanding 2.000s 99.911us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 51.721us 1 1 100.00
dma_csr_rw 2.000s 28.385us 1 1 100.00
dma_csr_aliasing 2.000s 40.268us 1 1 100.00
dma_same_csr_outstanding 2.000s 99.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 34.000s 1639.560us 1 1 100.00
dma_generic_stress 152.000s 19161.071us 1 1 100.00
dma_handshake_stress 351.000s 178131.117us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 10.000s 297.428us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 54.165us 1 1 100.00
dma_sec_cm 2.000s 11.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 162.000s 50189.641us 1 1 100.00
dma_longer_transfer 4.000s 386.578us 1 1 100.00
dma_stress_all_with_rand_reset 25.000s 708.624us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 43410522987535270827899995606255881267714693898518241050666241869679455065985 127
UVM_INFO @ 708624416ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---