Simulation Results: edn/edn0

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.04 %
  • code
  • 81.78 %
  • assert
  • 94.25 %
  • func
  • 49.09 %
  • block
  • 93.73 %
  • line
  • 96.64 %
  • branch
  • 86.46 %
  • toggle
  • 66.52 %
  • FSM
  • 77.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 19.753us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 26.548us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 24.109us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 8.000s 2375.465us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 161.773us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 50.672us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 24.109us 1 1 100.00
edn_csr_aliasing 2.000s 161.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 36.541us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 36.541us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 36.541us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 21.252us 1 1 100.00
alerts 1 1 100.00
edn_alert 3.000s 32.446us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 39.632us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 19.579us 1 1 100.00
edn_disable_auto_req_mode 2.000s 35.183us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 13.000s 330.303us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 21.802us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 421.440us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 36.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 36.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 26.548us 1 1 100.00
edn_csr_rw 2.000s 24.109us 1 1 100.00
edn_csr_aliasing 2.000s 161.773us 1 1 100.00
edn_same_csr_outstanding 2.000s 18.824us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 26.548us 1 1 100.00
edn_csr_rw 2.000s 24.109us 1 1 100.00
edn_csr_aliasing 2.000s 161.773us 1 1 100.00
edn_same_csr_outstanding 2.000s 18.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 9.000s 834.038us 1 1 100.00
edn_tl_intg_err 2.000s 210.081us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 23.644us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 3.000s 32.446us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 834.038us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 834.038us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 834.038us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 834.038us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 3.000s 32.446us 1 1 100.00
edn_sec_cm 9.000s 834.038us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 3.000s 32.446us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 210.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 79.000s 10755.608us 1 1 100.00