Simulation Results: edn/edn1

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.14 %
  • code
  • 84.72 %
  • assert
  • 98.18 %
  • func
  • 81.51 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 90.85 %
  • toggle
  • 95.12 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.260s 27.355us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.300s 78.784us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.110s 29.503us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.200s 529.252us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.050s 29.060us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.300s 19.134us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.110s 29.503us 1 1 100.00
edn_csr_aliasing 1.050s 29.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.480s 50.443us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.480s 50.443us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.480s 50.443us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.980s 44.568us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.630s 56.700us 1 1 100.00
errs 1 1 100.00
edn_err 1.230s 45.113us 1 1 100.00
disable 2 2 100.00
edn_disable 1.130s 17.823us 1 1 100.00
edn_disable_auto_req_mode 1.500s 39.327us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.960s 400.554us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.110s 70.818us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.370s 33.666us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.600s 26.713us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.600s 26.713us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.300s 78.784us 1 1 100.00
edn_csr_rw 1.110s 29.503us 1 1 100.00
edn_csr_aliasing 1.050s 29.060us 1 1 100.00
edn_same_csr_outstanding 1.360s 66.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.300s 78.784us 1 1 100.00
edn_csr_rw 1.110s 29.503us 1 1 100.00
edn_csr_aliasing 1.050s 29.060us 1 1 100.00
edn_same_csr_outstanding 1.360s 66.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.220s 1266.551us 1 1 100.00
edn_tl_intg_err 2.230s 560.953us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.220s 19.294us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.630s 56.700us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.220s 1266.551us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.220s 1266.551us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.220s 1266.551us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.220s 1266.551us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.630s 56.700us 1 1 100.00
edn_sec_cm 6.220s 1266.551us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.630s 56.700us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.230s 560.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 121.300s 41437.942us 1 1 100.00