Simulation Results: entropy_src/rng_16bits

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.01 %
  • code
  • 80.52 %
  • assert
  • 73.92 %
  • func
  • 49.58 %
  • block
  • 93.88 %
  • line
  • 97.57 %
  • branch
  • 85.61 %
  • toggle
  • 52.43 %
  • FSM
  • 86.46 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 26.762us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 45.180us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 17.172us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 9.000s 204.248us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 74.946us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 120.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 17.172us 1 1 100.00
entropy_src_csr_aliasing 3.000s 74.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 3.000s 26.762us 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
entropy_src_fw_ov 247.000s 6416.248us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 247.000s 6416.248us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 165.000s 13225.804us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
entropy_src_intr 21.000s 543.814us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
entropy_src_functional_alerts 8.000s 172.176us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 301.000s 14285.551us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 36.485us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 10.000s 111.198us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 14.343us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 233.976us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 5.000s 241.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 5.000s 241.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 45.180us 1 1 100.00
entropy_src_csr_rw 2.000s 17.172us 1 1 100.00
entropy_src_csr_aliasing 3.000s 74.946us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 73.684us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 45.180us 1 1 100.00
entropy_src_csr_rw 2.000s 17.172us 1 1 100.00
entropy_src_csr_aliasing 3.000s 74.946us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 73.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 113.541us 1 1 100.00
entropy_src_tl_intg_err 8.000s 697.350us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
entropy_src_cfg_regwen 2.000s 17.046us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
entropy_src_fw_ov 247.000s 6416.248us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 36.485us 1 1 100.00
entropy_src_sec_cm 2.000s 113.541us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 36.485us 1 1 100.00
entropy_src_sec_cm 2.000s 113.541us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 144.000s 14247.982us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 36.485us 1 1 100.00
entropy_src_sec_cm 2.000s 113.541us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 36.485us 1 1 100.00
entropy_src_sec_cm 2.000s 113.541us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 36.485us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 172.176us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 8.000s 697.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 444.000s 13022.427us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 43.000s 3673.633us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 92170952440431627607112557568857916554784205366177638330647651106287736894259 628
UVM_INFO @ 3673632894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:269) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
entropy_src_fw_ov 4938539529929373331884850585736380372382242890362402868016300739993305147401 804
UVM_INFO @ 6416248132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---