| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 0.920s | 20.473us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.710s | 1269.468us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.520s | 241.747us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.880s | 46.138us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.000s | 38.055us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 1.050s | 29.339us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 3.540s | 430.952us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.100s | 219.463us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.080s | 24.355us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 1.050s | 29.339us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.100s | 219.463us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.150s | 28.930us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.960s | 47.844us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.090s | 98.928us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.760s | 374.646us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.400s | 70.537us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.350s | 127.850us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 5.690s | 224.695us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 1.680s | 32.276us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 0.950s | 41.490us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 55.440s | 15788.454us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.920s | 23.593us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.890s | 59.634us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.700s | 54.652us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.700s | 54.652us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 1.050s | 29.339us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.520s | 100.700us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.100s | 219.463us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.000s | 38.055us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 1.050s | 29.339us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.520s | 100.700us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.100s | 219.463us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.000s | 38.055us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 3.160s | 501.778us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.220s | 297.265us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 3.160s | 501.778us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 0 | 1 | 0.00 | |||
| gpio_rand_straps | 0.870s | 1.337us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 0.990s | 4.378us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.880s | 19.668us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:243) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 2 test runs | |||
| gpio_stress_all | 75254672489435960654643051660944207088495678814357676188167016130561572206576 | 1344 |
UVM_INFO @ 15788453548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 111708515220222067865373340216567172831577306010700093573735073168841769532668 | 81 |
UVM_INFO @ 1336656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) | 1 test run | |||
| gpio_stress_all_with_rand_reset | 63139013177133543895146547272923318934999205406473610560553017094305975534383 | 86 |
UVM_INFO @ 4378014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|