Simulation Results: hmac

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.75 %
  • code
  • 83.24 %
  • assert
  • 97.17 %
  • func
  • 28.85 %
  • block
  • 97.55 %
  • line
  • 98.35 %
  • branch
  • 93.88 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.000s 443.280us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 21.553us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 69.061us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.000s 2374.089us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 58.554us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 12.837us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 69.061us 1 1 100.00
hmac_csr_aliasing 2.000s 58.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 14.000s 4326.516us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 40.000s 1432.985us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 16.000s 945.270us 1 1 100.00
hmac_test_sha384_vectors 31.000s 308.476us 1 1 100.00
hmac_test_sha512_vectors 428.000s 12361.494us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 443.024us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 421.811us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 3008.848us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 42.000s 3499.195us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 33.000s 8840.223us 1 1 100.00
error 1 1 100.00
hmac_error 89.000s 9159.060us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 73.000s 1827.733us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.000s 443.280us 1 1 100.00
hmac_long_msg 14.000s 4326.516us 1 1 100.00
hmac_back_pressure 40.000s 1432.985us 1 1 100.00
hmac_datapath_stress 33.000s 8840.223us 1 1 100.00
hmac_burst_wr 42.000s 3499.195us 1 1 100.00
hmac_stress_all 83.000s 29326.037us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.000s 443.280us 1 1 100.00
hmac_long_msg 14.000s 4326.516us 1 1 100.00
hmac_back_pressure 40.000s 1432.985us 1 1 100.00
hmac_datapath_stress 33.000s 8840.223us 1 1 100.00
hmac_wipe_secret 73.000s 1827.733us 1 1 100.00
hmac_test_sha256_vectors 16.000s 945.270us 1 1 100.00
hmac_test_sha384_vectors 31.000s 308.476us 1 1 100.00
hmac_test_sha512_vectors 428.000s 12361.494us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 443.024us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 421.811us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 3008.848us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.000s 443.280us 1 1 100.00
hmac_long_msg 14.000s 4326.516us 1 1 100.00
hmac_back_pressure 40.000s 1432.985us 1 1 100.00
hmac_datapath_stress 33.000s 8840.223us 1 1 100.00
hmac_burst_wr 42.000s 3499.195us 1 1 100.00
hmac_error 89.000s 9159.060us 1 1 100.00
hmac_wipe_secret 73.000s 1827.733us 1 1 100.00
hmac_test_sha256_vectors 16.000s 945.270us 1 1 100.00
hmac_test_sha384_vectors 31.000s 308.476us 1 1 100.00
hmac_test_sha512_vectors 428.000s 12361.494us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 443.024us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 421.811us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 3008.848us 1 1 100.00
hmac_stress_all 83.000s 29326.037us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 83.000s 29326.037us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 14.148us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 34.146us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 381.933us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 381.933us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 21.553us 1 1 100.00
hmac_csr_rw 2.000s 69.061us 1 1 100.00
hmac_csr_aliasing 2.000s 58.554us 1 1 100.00
hmac_same_csr_outstanding 3.000s 130.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 21.553us 1 1 100.00
hmac_csr_rw 2.000s 69.061us 1 1 100.00
hmac_csr_aliasing 2.000s 58.554us 1 1 100.00
hmac_same_csr_outstanding 3.000s 130.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 319.895us 1 1 100.00
hmac_tl_intg_err 4.000s 170.508us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 170.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.000s 443.280us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 7.000s 194.756us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 120.000s 2548.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 9.000s 548.646us 1 1 100.00