Simulation Results

Simulation Results: i2c

14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.38 %

code
85.65 %

assert
97.46 %

func
82.04 %

block
96.00 %

line
95.40 %

branch
92.83 %

toggle
72.35 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	107.000s	1333.816us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	13.000s	3958.584us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	54.214us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	76.001us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	11055.635us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	102.296us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	56.371us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	76.001us	1	1	100.00
	i2c_csr_aliasing	2.000s	102.296us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	106.269us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3601.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	27.000s	970.565us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	16.393us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1471.000s	1741.945us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	76.670us	1	1	100.00
	i2c_host_fifo_fmt_empty	45.000s	1380.208us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	159.142us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	2744.000s	3915.952us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1905.787us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	3.000s	203.139us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	1804.445us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	481.309us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	6.000s	790.441us	1	1	100.00
	i2c_target_intr_smoke	10.000s	7129.679us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	555.987us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	232.894us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	6.000s	790.441us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	1107.317us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	129.000s	3391.083us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	3090.709us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	52.000s	10155.864us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	1727.438us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	89.303us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	27.000s	970.565us	1	1	100.00
	i2c_host_perf_precise	157.000s	23413.515us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	1905.787us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	7.000s	475.982us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	963.523us	1	1	100.00
	i2c_target_nack_acqfull_addr	5.000s	541.787us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	168.875us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.000s	630.901us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	2191.495us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	18.140us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	29.007us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	5.000s	137.655us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	5.000s	137.655us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	54.214us	1	1	100.00
	i2c_csr_rw	2.000s	76.001us	1	1	100.00
	i2c_csr_aliasing	2.000s	102.296us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	94.021us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	54.214us	1	1	100.00
	i2c_csr_rw	2.000s	76.001us	1	1	100.00
	i2c_csr_aliasing	2.000s	102.296us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	94.021us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	4.000s	1999.805us	1	1	100.00
	i2c_sec_cm	1.000s	694.754us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	4.000s	1999.805us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	31.000s	755.349us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	216.764us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	15.000s	1960.649us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				5 test runs
	i2c_host_fifo_watermark	71872491339367042894130582579999564681954078773909690049780465673597601355411	None
	i2c_host_stress_all	26890935653778330170606439453659002706169537603502384190511816010083522240693	None
	i2c_target_stress_wr	36554038477573535445793031312174885158541990698286648317715083514700169238367	None
	i2c_target_intr_stress_wr	69680204216166401720826878851351082869104084326175595301834847558652232785053	None
	i2c_target_stress_all	69379242378340587174099619258946999176707938457388717428241772569315678708396	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	8720117756803586486586803424348547274989738554496363297376420850875062058075	129	UVM_INFO @ 106269190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	22730455845355373485033055065357176331966829566871989773215127500039910955231	93	UVM_INFO @ 1804445393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	42538464952042444966282575172137922794097231446688064243725692131947169426671	87	UVM_INFO @ 216764020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	41451698759521885099601936638275225546035111788852136638233040545651337159626	88	UVM_INFO @ 10155864440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	37185582277994166387609665927197763008829186202030230341333866852863245715277	112	UVM_INFO @ 755348691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1210) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	67446043098306205924891903171124176855282027196737923567506863727618914161410	95	UVM_INFO @ 1960648604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---