Simulation Results: lc_ctrl/volatile_unlock_disabled

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.08 %
  • code
  • 89.69 %
  • assert
  • 96.83 %
  • func
  • 77.74 %
  • block
  • 95.80 %
  • line
  • 95.70 %
  • branch
  • 89.31 %
  • toggle
  • 83.25 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 40.049us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 49.525us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.372us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 109.195us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 18.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 174.997us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 14.372us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 18.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 232.508us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 59.882us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 558.124us 1 1 100.00
lc_ctrl_jtag_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 5771.703us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 11.000s 870.047us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 1946.003us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 686.319us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 822.580us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.000s 900.527us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 226.971us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 302.662us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 100.941us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 95.286us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 389.647us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 42.351us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.311s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 20.873us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 142.409us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 142.409us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 49.525us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.372us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 18.359us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 88.453us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 49.525us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.372us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 18.359us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 88.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 87.272us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 87.272us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 232.508us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 2240.884us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 558.124us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 425.508us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 969.231us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 969.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 62575031123382343796956041699121382060561833107301885315261723341996302443578 None
lc_ctrl_state_post_trans 37937728538729645216004227371390373321472442210493469778217742164935691067337 None
lc_ctrl_prog_failure 87579246760584447674640319485562911215832327500045795154756097473291015326610 None
lc_ctrl_errors 96710770515376622005508754286553265516058956352731239415100094906471678557044 None
lc_ctrl_jtag_state_failure 48975297961428041157888421098709476112822664885668449938098291735608769839423 None
lc_ctrl_jtag_state_post_trans 95715349418382952653433908139037858041539599301795964213180890686451102988295 None
lc_ctrl_jtag_prog_failure 17156329063125133642158970656913367926247224882978721974766319628736376792461 None
lc_ctrl_jtag_errors 73619785404865725566732757668133406014985875382095006928007648110009240661534 None
lc_ctrl_sec_mubi 17596644873401474475662992552281637298534892985164786786236211328325810512867 None
lc_ctrl_stress_all 46668077960962271243399578755217948351107678289489631644246384006874956085129 None
lc_ctrl_stress_all_with_rand_reset 20420583414256994235115750291244980031253520669979111119835692943281735824518 None