Simulation Results: lc_ctrl/volatile_unlock_enabled

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.18 %
  • code
  • 90.51 %
  • assert
  • 95.97 %
  • func
  • 78.06 %
  • block
  • 96.48 %
  • line
  • 97.27 %
  • branch
  • 91.08 %
  • toggle
  • 83.20 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 290.479us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 44.966us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 21.792us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 129.605us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 106.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 79.221us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 21.792us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 106.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 478.627us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 15.956us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 1239.969us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 10.000s 3393.944us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 6.000s 5514.039us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 1193.826us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 600.901us 1 1 100.00
lc_ctrl_jtag_csr_rw 4.000s 537.445us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 2418.100us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 96.204us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 54.623us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 55.844us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 54.782us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 668.448us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 22.325us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.097s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 21.616us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 163.496us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 163.496us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 44.966us 1 1 100.00
lc_ctrl_csr_rw 2.000s 21.792us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 106.832us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 31.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 44.966us 1 1 100.00
lc_ctrl_csr_rw 2.000s 21.792us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 106.832us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 31.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 92.939us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 92.939us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 478.627us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 439.226us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1239.969us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 720.964us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 333.859us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 333.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 92206849984442445494975795523696647090113981471222736815620310629274303995246 None
lc_ctrl_state_post_trans 18590833629264796398301046242110528209842727526463324006762033262777993368571 None
lc_ctrl_prog_failure 17072591349554954244602745667487158925789161305323205879339137267370933270323 None
lc_ctrl_errors 80856201933588827021222879539809729095818314639960350590062557593383311327837 None
lc_ctrl_jtag_state_failure 50816662773765329118362301512633470952440319755576668969705437025491034979856 None
lc_ctrl_jtag_state_post_trans 102840795210010461514402229031189886375549886719934086808346476208021179460171 None
lc_ctrl_jtag_prog_failure 83339345934309436312650531556598113544645649870831091453636213506559300268840 None
lc_ctrl_jtag_errors 14012672076612454687483265866818389747235695235100566225380953911919983520494 None
lc_ctrl_sec_mubi 103773640574450061484134467082330552708835532215151373429935801134308786432966 None
lc_ctrl_stress_all 38299720115151858927736544622869459008583273290518216130360736287562504749927 None
lc_ctrl_stress_all_with_rand_reset 39902187910453856813390334133319215595580468773734842060566937637931636272536 None