Simulation Results: mbx

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.38 %
  • code
  • 89.59 %
  • assert
  • 96.96 %
  • func
  • 78.60 %
  • block
  • 97.01 %
  • line
  • 96.84 %
  • branch
  • 92.25 %
  • toggle
  • 79.67 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 67.000s 10235.713us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 15.613us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 42.417us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 147.021us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 36.193us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 6.641us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 42.417us 1 1 100.00
mbx_csr_aliasing 2.000s 36.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 2.000s 29.974us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 147.000s 6487.131us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 26.000s 7724.891us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 12.000s 790.964us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 197.414us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 15.426us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 6.372us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 6.372us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.613us 1 1 100.00
mbx_csr_rw 2.000s 42.417us 1 1 100.00
mbx_csr_aliasing 2.000s 36.193us 1 1 100.00
mbx_same_csr_outstanding 2.000s 287.285us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.613us 1 1 100.00
mbx_csr_rw 2.000s 42.417us 1 1 100.00
mbx_csr_aliasing 2.000s 36.193us 1 1 100.00
mbx_same_csr_outstanding 2.000s 287.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 3.000s 1821.640us 1 1 100.00
mbx_sec_cm 2.000s 75.345us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:718) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 34470325251260188474741922484231165423952494001801418709099170539954472639958 85
TL item was: req: (cip_tl_seq_item@18412) { a_addr: 'hd444aad4 a_data: 'h65543675 a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'h87 a_opcode: 'h1 a_user: 'h25145 d_param: 'h0 d_source: 'h87 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6371903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 56173861846185672247488446084929150954739254472459174495827887490008346137216 86
TL item was: req: (cip_tl_seq_item@20540) { a_addr: 'hd49ac2b0 a_data: 'h957448ac a_mask: 'hb a_size: 'h2 a_param: 'h0 a_source: 'ha3 a_opcode: 'h1 a_user: 'h26a49 d_param: 'h0 d_source: 'ha3 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6641019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 50103610003127569937538384411744626378512844280849929563658745970184818458379 141
UVM_INFO @ 29974379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---