Simulation Results: otbn

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 85.92 %
  • assert
  • 89.55 %
  • func
  • 97.88 %
  • block
  • 99.20 %
  • line
  • 99.41 %
  • branch
  • 94.25 %
  • toggle
  • 83.81 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
82.35%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 145.960us 1 1 100.00
otbn_smoke_vectorized 10.000s 39.431us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 7.000s 26.632us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 39.602us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 91.401us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 15.606us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 385.027us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 39.602us 1 1 100.00
otbn_csr_aliasing 5.000s 15.606us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 128.000s 5559.179us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 54.000s 1254.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 46.000s 88.341us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 20.000s 49.927us 0 1 0.00
wfi 1 3 33.33
otbn_wfi_smoke 7.000s 49.956us 0 1 0.00
otbn_wfi_sec_wipe 9.000s 18.526us 1 1 100.00
otbn_wfi_back_to_back 6.000s 4.591us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 92.000s 1598.861us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 109.000s 931.825us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 60.770us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 118.048us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 45.089us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 236.892us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 17.419us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 9.000s 317.667us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 9.000s 317.667us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 7.000s 26.632us 1 1 100.00
otbn_csr_rw 4.000s 39.602us 1 1 100.00
otbn_csr_aliasing 5.000s 15.606us 1 1 100.00
otbn_same_csr_outstanding 7.000s 47.819us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 7.000s 26.632us 1 1 100.00
otbn_csr_rw 4.000s 39.602us 1 1 100.00
otbn_csr_aliasing 5.000s 15.606us 1 1 100.00
otbn_same_csr_outstanding 7.000s 47.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 14.000s 37.136us 1 1 100.00
otbn_dmem_err 12.000s 41.352us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 13.000s 60.112us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 38.816us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 48.878us 1 1 100.00
otbn_urnd_err 7.000s 118.955us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 123.187us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 11.000s 18.147us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 14.000s 45.601us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
otbn_tl_intg_err 27.000s 144.334us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 36.000s 1992.099us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 145.960us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 12.000s 41.352us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 14.000s 37.136us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 27.000s 144.334us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 60.770us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 14.000s 37.136us 1 1 100.00
otbn_dmem_err 12.000s 41.352us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 118.048us 1 1 100.00
otbn_illegal_mem_acc 7.000s 123.187us 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 14.000s 37.136us 1 1 100.00
otbn_dmem_err 12.000s 41.352us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 118.048us 1 1 100.00
otbn_illegal_mem_acc 7.000s 123.187us 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 60.770us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 14.000s 37.136us 1 1 100.00
otbn_dmem_err 12.000s 41.352us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 118.048us 1 1 100.00
otbn_illegal_mem_acc 7.000s 123.187us 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 10.000s 21.585us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 62.849us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 89.000s 400.255us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 89.000s 400.255us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 12.000s 42.797us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 13.000s 215.388us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 55.379us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 55.379us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 10.318us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 92.000s 1598.861us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 26.000s 37.172us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 66.959us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 446.000s 1744.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 80.000s 272.045us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 21533956911113633046590010668761602224989387801470218531814601565661253910719 113
UVM_INFO @ 49956117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 79806224267188754537655211182402273265505248585277750508836719370789275508518 113
UVM_INFO @ 4591222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 80569048568902304552461259320226479163314016624135467793347290927785818602895 254
UVM_INFO @ 49926963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 109975953465843613989347997211131785850084055977154178974961050376637204368655 161
UVM_INFO @ 272045482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---