Simulation Results: otp_ctrl

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.98 %
  • code
  • 68.20 %
  • assert
  • 91.67 %
  • func
  • 50.07 %
  • line
  • 85.06 %
  • branch
  • 79.28 %
  • cond
  • 83.96 %
  • toggle
  • 64.80 %
  • FSM
  • 27.91 %
Validation stages
V1
100.00%
V2
50.00%
V2S
33.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.370s 212.799us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.390s 193.846us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.610s 59.125us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.210s 705.268us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 107.006us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.380s 171.915us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.610s 59.125us 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 107.006us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.320s 96.329us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.310s 60.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 182.140s 30030.056us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.850s 109.667us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 2.950s 380.291us 0 1 0.00
otp_ctrl_check_fail 7.100s 1785.682us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 14.340s 1154.218us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 8.940s 1638.633us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 23.430s 8199.124us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 10.250s 1298.343us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.860s 85.252us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 18.180s 5970.183us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 15.320s 7096.187us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.190s 88.407us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.460s 346.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.520s 200.072us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.520s 200.072us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.390s 193.846us 1 1 100.00
otp_ctrl_csr_rw 2.610s 59.125us 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 107.006us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.540s 103.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.390s 193.846us 1 1 100.00
otp_ctrl_csr_rw 2.610s 59.125us 1 1 100.00
otp_ctrl_csr_aliasing 3.270s 107.006us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.540s 103.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
otp_ctrl_tl_intg_err 17.860s 1837.566us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 17.860s 1837.566us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_dai_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
sec_cm_part_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_ctrl_macro_errs 2.860s 85.252us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
sec_cm_timer_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_dai_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
sec_cm_part_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_ctrl_macro_errs 2.860s 85.252us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
sec_cm_timer_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 7.980s 796.686us 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.850s 109.667us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 7.100s 1785.682us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 15.810s 6398.294us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.750s 2026.347us 0 1 0.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 14.340s 1154.218us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 17.880s 3193.186us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.860s 85.252us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 116.510s 68926.142us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 46.410s 1452.031us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_background_chks 104754388027104838419512697759350123030704185008680540948865701175670027466452 854
UVM_INFO @ 380291228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 100011579032449743861439382577879488248203837047335188226201008034168573690908 4518
UVM_INFO @ 1298343167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 30712969516270675026806602150010573780393819394352956311859447806496617300866 4552
UVM_INFO @ 1638633445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_init_fail 41149872880037798643097078197575306294423343621592051501359333570494605922693 331
UVM_INFO @ 109667452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 2580207529830588089304905099795603417838189534412117355717505366283492977354 9866
UVM_INFO @ 1154217670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 2 test runs
otp_ctrl_parallel_lc_esc 107355785521966710574259186491802723939983825039784245526923901667386068164579 2741
UVM_INFO @ 796685635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 97005070188483555857521638037326243606089809188379356530221748571038038241188 6082
UVM_INFO @ 7096186854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 87931760464991647366253629624613506886418763349612173371441912151714124828693 110261
UVM_INFO @ 30030055878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 65198941077831968374364517847528487840831457710993590182074567768913434079869 95
UVM_INFO @ 68926142167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 95197443290680792092933211095938949452476383762376263500387224686221303425892 358
UVM_INFO @ 1785681960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error 1 test run
otp_ctrl_macro_errs 110065505728817574672587379632702012092387785557437908620466196689467272828984 678
UVM_INFO @ 85251992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 80317411619495529245970089928655218985803134291020283863944415527589928947816 14212
UVM_INFO @ 1452031230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 49978755684107106646368102914246072646518574368749713860315720642403809795472 192
UVM_INFO @ 2026346894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---