Simulation Results: rom_ctrl/32kb

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.66 %
  • code
  • 79.47 %
  • assert
  • 97.53 %
  • func
  • 85.99 %
  • block
  • 78.24 %
  • line
  • 78.74 %
  • branch
  • 78.60 %
  • toggle
  • 84.35 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 266.667us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 68.217us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 61.226us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 201.049us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 54.579us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 85.430us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 61.226us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 54.579us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.000s 55.432us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 67.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 165.618us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.000s 168.314us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 475.746us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 76.606us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 372.239us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 372.239us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 68.217us 1 1 100.00
rom_ctrl_csr_rw 2.000s 61.226us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 54.579us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 80.211us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 68.217us 1 1 100.00
rom_ctrl_csr_rw 2.000s 61.226us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 54.579us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 80.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 104.984us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 139.000s 1300.290us 1 1 100.00
rom_ctrl_tl_intg_err 34.000s 204.814us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 139.000s 1300.290us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 139.000s 1300.290us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 139.000s 1300.290us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 139.000s 1300.290us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 266.667us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 266.667us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 266.667us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 34.000s 204.814us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 5.000s 475.746us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 104.984us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 139.000s 1300.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 5.000s 180.238us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 38850212431940551514915939910200015457663622302453900100964313867689313895017 88
UVM_INFO @ 165617699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 56063114829376330673939293293199612323169626046258220167541836330846261646426 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 65538423761927400027455787712631310692480882220250103769175533816868295776550 90
UVM_INFO @ 180237744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---