Simulation Results: rom_ctrl/64kb

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.94 %
  • code
  • 79.21 %
  • assert
  • 97.23 %
  • func
  • 78.38 %
  • block
  • 77.99 %
  • line
  • 78.48 %
  • branch
  • 77.91 %
  • toggle
  • 84.27 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 395.018us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 85.855us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 59.532us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 124.198us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 68.028us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 61.417us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 59.532us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 68.028us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 54.565us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 57.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 7.894us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.000s 1104.563us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 2645.445us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 53.647us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 117.060us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 117.060us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 85.855us 1 1 100.00
rom_ctrl_csr_rw 3.000s 59.532us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 68.028us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 64.881us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 85.855us 1 1 100.00
rom_ctrl_csr_rw 3.000s 59.532us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 68.028us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 64.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 179.493us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 119.000s 234.850us 1 1 100.00
rom_ctrl_tl_intg_err 59.000s 712.699us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 119.000s 234.850us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 119.000s 234.850us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 119.000s 234.850us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 119.000s 234.850us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 395.018us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 395.018us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 395.018us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 59.000s 712.699us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 9.000s 2645.445us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 179.493us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 119.000s 234.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 32.000s 7722.140us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 79011242694262901950312035928702679826928184294249174764732165631014849920230 88
UVM_INFO @ 7893676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
rom_ctrl_corrupt_sig_fatal_chk 89543130581456230857669559140117744399535475445363221995863557248543983051972 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 63254399716736414490252392022307105427869648930233461307590494057296439244241 141
UVM_INFO @ 7722140141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---