Simulation Results: rstmgr

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.75 %
  • code
  • 99.25 %
  • assert
  • 98.53 %
  • func
  • 95.48 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.840s 70.992us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.530s 94.479us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.250s 36.071us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.270s 236.813us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.050s 35.781us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.440s 97.812us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.250s 36.071us 1 1 100.00
rstmgr_csr_aliasing 1.050s 35.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.630s 86.920us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.470s 43.417us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.440s 61.089us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.250s 627.174us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.250s 627.174us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.250s 627.174us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.250s 627.174us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.230s 2361.971us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.230s 35.507us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.900s 39.855us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.900s 39.855us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.530s 94.479us 1 1 100.00
rstmgr_csr_rw 1.250s 36.071us 1 1 100.00
rstmgr_csr_aliasing 1.050s 35.781us 1 1 100.00
rstmgr_same_csr_outstanding 1.230s 36.497us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.530s 94.479us 1 1 100.00
rstmgr_csr_rw 1.250s 36.071us 1 1 100.00
rstmgr_csr_aliasing 1.050s 35.781us 1 1 100.00
rstmgr_same_csr_outstanding 1.230s 36.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 40.620s 6892.235us 1 1 100.00
rstmgr_tl_intg_err 7.590s 734.329us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 40.620s 6892.235us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 40.620s 6892.235us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 7.590s 734.329us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.570s 61.376us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.270s 475.116us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.730s 291.169us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 40.620s 6892.235us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 36.071us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 36.071us 1 1 100.00