Simulation Results: spi_device/1r1w

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.23 %
  • code
  • 89.52 %
  • assert
  • 95.40 %
  • func
  • 70.76 %
  • block
  • 98.35 %
  • line
  • 98.75 %
  • branch
  • 97.01 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 174.000s 49847.581us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 241.544us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 39.088us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 35.000s 1555.638us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.000s 149.750us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 69.750us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 39.088us 1 1 100.00
spi_device_csr_aliasing 5.000s 149.750us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 36.759us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 51.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 14.717us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 5.768us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.791us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 5.000s 147.930us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 5.000s 147.930us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.000s 1104.886us 1 1 100.00
spi_device_tpm_sts_read 3.000s 70.036us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.000s 14.163us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 13.000s 2536.020us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 693.435us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 693.435us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.000s 913.094us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.000s 913.094us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.000s 913.094us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.000s 913.094us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.000s 913.094us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 17.000s 1040.316us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 30.000s 695.654us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 30.000s 695.654us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 30.000s 695.654us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 14.000s 3997.019us 1 1 100.00
spi_device_read_buffer_direct 14.000s 1112.031us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 30.000s 695.654us 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 85.000s 4150.393us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.000s 303.618us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.000s 303.618us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 381.000s 27310.619us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 174.000s 49847.581us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 172.000s 53228.882us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 69.000s 5184.865us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 42.190us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 18.363us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 60.512us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 60.512us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 241.544us 1 1 100.00
spi_device_csr_rw 2.000s 39.088us 1 1 100.00
spi_device_csr_aliasing 5.000s 149.750us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 387.462us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 241.544us 1 1 100.00
spi_device_csr_rw 2.000s 39.088us 1 1 100.00
spi_device_csr_aliasing 5.000s 149.750us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 387.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 365.777us 1 1 100.00
spi_device_tl_intg_err 11.000s 1443.351us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.000s 1443.351us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 33346560813490103466961499820316194410674736971866420175146948768835200211082 87
UVM_ERROR @ 5226252 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994] not found within the scope .
UVM_ERROR @ 5226252 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[994] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 11396296924079885270071643816540826412279788483217651493973612920419525528897 85
UVM_ERROR @ 1172517 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12e [100101110] vs 0x0 [0])
UVM_ERROR @ 1192517 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x43 [1000011] vs 0x0 [0])
UVM_ERROR @ 1245517 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa9 [10101001] vs 0x0 [0])
UVM_ERROR @ 1298517 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4f [1001111] vs 0x0 [0])