Simulation Results: sram_ctrl/ret

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.60 %
  • code
  • 81.74 %
  • assert
  • 97.67 %
  • func
  • 95.40 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 45.280us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 26.906us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.904us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 633.735us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.687us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 129.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 21.904us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.687us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 15.000s 4811.726us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 116.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 1961.505us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 118.000s 2054.851us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 10.000s 2236.309us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 496.818us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 10.000s 2402.418us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 16.000s 2398.917us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 253.419us 1 1 100.00
sram_ctrl_partial_access_b2b 386.000s 44856.312us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 66.299us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 41.926us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 88.043us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 140.262us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 45.022us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 45.280us 1 1 100.00
sram_ctrl_partial_access 2.000s 253.419us 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 496.818us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 40.000s 2867.557us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 42.674us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 29.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 29.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 26.906us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.904us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.687us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 36.148us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 26.906us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.904us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.687us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 36.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 829.538us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1535.927us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 267.803us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1535.927us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 267.803us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 140.262us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 140.262us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.904us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 16.000s 2398.917us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 2398.917us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 2398.917us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 10.000s 2402.418us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 829.538us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.280us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.280us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 16.000s 2398.917us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1535.927us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 10.000s 2402.418us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1535.927us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1535.927us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 45.280us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1535.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 134.000s 4896.440us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 32926491112442979572102726697613070860873587472536787653385318057212183774006 None
sram_ctrl_mubi_enc_err 7513792995617427365404997422053242618399913274265547851995565701934384254274 None